利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

33 条记录 (耗时 0.017 秒)

    Plasma display panel having dedicated priming electrodes outside display area and driving method for same panel
    2.
    发明授权
    Plasma display panel having dedicated priming electrodes outside display area and driving method for same panel 失效
    等离子显示面板具有专用的底漆电极在显示区域外面，同时驱动方法

    公开(公告)号：US6144348A

    公开(公告)日：2000-11-07

    申请号：US906111

    申请日：1997-08-05

    申请人： Yoshikazu Kanazawa ,  Fumitaka Asami

    发明人： Yoshikazu Kanazawa ,  Fumitaka Asami

    IPC分类号： G09G3/288 ,  G09G3/291 ,  G09G3/292 ,  G09G3/293 ,  G09G3/298 ,  H01J11/12 ,  H01J11/14 ,  H01J11/22 ,  H01J11/24 ,  H01J11/26 ,  H01J11/28 ,  H01J11/34 ,  H01J11/36 ,  H01J11/38 ,  H01J11/44 ,  G09G3/28

    CPC分类号： G09G3/296 ,  G09G3/2927 ,  G09G3/2932 ,  G09G2320/0228

    摘要： A plasma display panel and driving method thereof perform addressing at a high speed and a low voltage without deteriorating contrast. Priming electrodes forming priming cells are located outside but adjacent a display area. Glow occurring in the priming cells is intercepted. When priming discharge is induced at a reset step, voltages lower than a discharge start voltage are applied to first (X) and second (Y) electrodes and third (address) electrodes respectively. Despite the voltages being lower than the discharge start voltage, once discharge is induced in the priming cells, discharge starts in adjoining cells. The discharge then spreads successively over all the cells, thus inducing discharge in all the cells. Consequently, wall charge is produced in all the cells.

    摘要翻译： 等离子体显示面板及其驱动方法以高速低电压进行寻址，而不会降低对比度。 形成起始电池的起始电极位于显示区域外部但邻近显示区域。 在引发细胞中发生的辉光被截获。 当在复位步骤中引发起动放电时，分别向第一（X）和第二（Y）电极和第三（地址）电极施加低于放电开始电压的电压。 尽管电压低于放电开始电压，一旦在引发电池中引发放电，则在邻接的电池中开始放电。 然后放电遍及所有电池，从而在所有电池中引起放电。 因此，在所有电池中产生壁电荷。

    Semiconductor delay circuit device
    3.
    发明授权
    Semiconductor delay circuit device 失效
    半导体延迟电路器件

    公开(公告)号：US5391904A

    公开(公告)日：1995-02-21

    申请号：US080651

    申请日：1993-06-22

    申请人： Fumitaka Asami ,  Shinya Udo

    发明人： Fumitaka Asami ,  Shinya Udo

    IPC分类号： H01L27/092 ,  H01L27/112 ,  H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L27/0925 ,  H01L27/112

    摘要： A semiconductor delay circuit device comprises a pair of transistors of the same conduction type having source regions that are arranged adjacent to each other and facing each other, and a substrate contact diffusion region whose conduction type is opposite to that of the source regions. The substrate contact diffusion region extends between the source regions. Therefore, the source regions of the transistors do not influence each other.

    摘要翻译： 半导体延迟电路器件包括具有彼此相邻布置并且彼此相对的源极区的相同导电类型的一对晶体管，以及导电类型与源极区相反的衬底接触扩散区域。 衬底接触扩散区域在源极区域之间延伸。 因此，晶体管的源极区域不会相互影响。

    Noise pulse suppressing circuit in digital system
    4.
    发明授权
    Noise pulse suppressing circuit in digital system 失效
    数字系统中的噪声脉冲抑制电路

    公开(公告)号：US4786823A

    公开(公告)日：1988-11-22

    申请号：US39337

    申请日：1987-04-17

    申请人： Masato Abe ,  Fumitaka Asami

    发明人： Masato Abe ,  Fumitaka Asami

    IPC分类号： H03H17/00 ,  H03K3/13 ,  H03K5/1252 ,  H03K5/22

    CPC分类号： H03K5/1252

    摘要： Noise pulses having both polarities which are superposed on an input signal having a binary state of H/L levels forming a rectangular waveform, are suppressed or eliminated before transferring the input signal to an output stage. A noise pulse suppressing circuit is provided which comprises a latch circuit, a counter circuit, and a logic circuit including NAND gates and INVERTERs. For the latch circuit and the counter circuit, D-type flip-flops are also utilized. The input signal is inputted to a data input terminal of a flip-flop of the latch circuit and outputted from the data output terminal thereof. The latch circuits are triggered by a pulse signal applied to a clock terminal thereof. The above triggering pulse signal is generated by the counter circuit and the logic circuit, and it has a short pulse waveform responding to the input signal but delayed. No pulse in the output is produced which corresponds to the noise pulses in the input signal.

    摘要翻译： 在将输入信号传送到输出级之前，抑制或消除具有叠加在形成矩形波形的H / L电平的二进制状态的输入信号上的两个极性的噪声脉冲。 提供一种噪声脉冲抑制电路，其包括锁存电路，计数器电路和包括与非门和反相器的逻辑电路。 对于锁存电路和计数器电路，也使用D型触发器。 输入信号被输入到锁存电路的触发器的数据输入端，并从其数据输出端输出。 锁存电路由施加到其时钟端的脉冲信号触发。 上述触发脉冲信号由计数器电路和逻辑电路产生，并且具有响应输入信号但延迟的短脉冲波形。 不产生与输入信号中的噪声脉冲相对应的输出脉冲。

    Display apparatus
    5.
    发明授权
    Display apparatus 失效
    显示装置

    公开(公告)号：US06496166B1

    公开(公告)日：2002-12-17

    申请号：US09608150

    申请日：2000-06-30

    申请人： Makoto Onozawa ,  Yuji Sano ,  Michitaka Ohsawa ,  Takashi Sasaki ,  Noboru Akiyama ,  Fumitaka Asami ,  Kazuo Yoshiikawa ,  Hitoshi Hirakawa ,  Tomokatsu Kishi ,  Toyoshi Kawada

    发明人： Makoto Onozawa ,  Yuji Sano ,  Michitaka Ohsawa ,  Takashi Sasaki ,  Noboru Akiyama ,  Fumitaka Asami ,  Kazuo Yoshiikawa ,  Hitoshi Hirakawa ,  Tomokatsu Kishi ,  Toyoshi Kawada

    IPC分类号： G09G328

    CPC分类号： G09G3/2965 ,  G09G3/2927 ,  G09G3/293 ,  G09G3/294 ,  G09G3/296

    摘要： As is obvious from the description in the specification and the attached drawings, the present invention provides a display apparatus for displaying an image on a display panel by turning on pixels of said display panel, said display apparatus comprising: a display panel provided with: address electrodes driven by address pulses based on a video input signal; and sustain electrodes crossing said address electrodes and sandwiching electrical discharging units of pixels with said address electrodes and driven by sustain pulses; a sustain-electrode drive circuit for generating said sustain pulses and scan pulses, provided with a common circuit for generating said sustain pulses or said scan pulses in response to an operating state thereof and for supplying said scan pulses and said sustain pulses to said sustain electrodes.

    摘要翻译： 从说明书和附图的说明可以看出，本发明提供一种显示装置，用于通过打开所述显示面板的像素在显示面板上显示图像，所述显示装置包括：显示面板，设置有：地址 基于视频输入信号的寻址脉冲驱动的电极; 并维持与所述寻址电极交叉的电极，并用所述寻址电极夹持像素的放电单元并由维持脉冲驱动; 用于产生所述维持脉冲和扫描脉冲的维持电极驱动电路，设置有用于响应于其工作状态产生所述维持脉冲或所述扫描脉冲的公共电路，并用于将所述扫描脉冲和所述维持脉冲提供给所述维持电极 。

    Synchronous separation circuit
    7.
    发明授权
    Synchronous separation circuit 失效
    同步分离电路

    公开(公告)号：US4999708A

    公开(公告)日：1991-03-12

    申请号：US299534

    申请日：1989-01-23

    申请人： Tetsuo Aoki ,  Fumitaka Asami

    发明人： Tetsuo Aoki ,  Fumitaka Asami

    IPC分类号： H04N5/10

    CPC分类号： H04N5/10

    摘要： A synchronous separation circuit used in a television video circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal from a composite synchronizing signal has: a unit for generating a clock signal used as a reference signal and having a frequency higher than the frequency of the horizontal synchronizing signal; a unit for counting the clock signal from a front edge of a pulse contained in the composite synchronizing signal; a unit for obtaining a horizontal synchronous separation and for determining a counting term and outputting the horizontal synchronizing signal after the counting unit counts from the front edge of the horizontal synchronizing signal to a predetermined number; and a unit for obtaining a vertical synchronous separation and for latching the composite synchronizing signal based on an output of the counting unit, separate the vertical synchronizing signal from the composite synchronizing signal.

    Phase comparator circuit
    8.
    发明授权
    Phase comparator circuit 失效
    相位比较电路

    公开(公告)号：US4904948A

    公开(公告)日：1990-02-27

    申请号：US167712

    申请日：1988-03-14

    申请人： Fumitaka Asami

    发明人： Fumitaka Asami

    IPC分类号： H03D13/00 ,  H03K5/26

    CPC分类号： H03L7/0891 ,  H03K5/26

    摘要： A phase comparator circuit for comparing a phase of a first input signal with a second input signal and outputting a first output signal and a second output signal in accordance with a result of the comparison, and comprising two flip-flop circuits and a latch circuit, whereby, when the first and second input signals are in-phase, both first and second output signals are output.

    Lock detecting circuit for phase-locked loop frequency synthesizer
    9.
    发明授权
    Lock detecting circuit for phase-locked loop frequency synthesizer 失效
    锁相环频率合成器的锁定检测电路

    公开(公告)号：US4437072A

    公开(公告)日：1984-03-13

    申请号：US420633

    申请日：1982-09-21

    申请人： Fumitaka Asami

    发明人： Fumitaka Asami

    IPC分类号： H03L7/18 ,  H03K5/26 ,  H03L7/08 ,  H03L7/089 ,  H03L7/095 ,  H04B1/10

    CPC分类号： H03K5/26 ,  H03L7/0891 ,  H03L7/095 ,  Y10S331/02

    摘要： A phase-locked loop circuit comprising a reference oscillator (1), a reference frequency divider (2) for dividing the output signal of the reference oscillator, a programmable frequency divider (3), a phase comparator (4) for monitoring the difference in phase between the output signal of the two frequency dividers, a lock detector (11) for generating a first signal which is pulse-shaped or rectangular when the above-mentioned difference in phase is generated, and a digital signal maintaining circuit (100) for converting the first signal into a second directed current signal.

    摘要翻译： 一种锁相环电路，包括参考振荡器（1），用于分频基准振荡器的输出信号的参考分频器（2），可编程分频器（3），相位比较器（4） 两个分频器的输出信号之间的相位，当产生上述相位差时产生脉冲形或矩形的第一信号的锁定检测器（11），以及用于产生第二信号的数字信号维持电路 将第一信号转换成第二定向电流信号。