发明授权
- 专利标题: Five-transistor static memory cell implemental in CMOS/bulk
- 专利标题(中): 五晶体管静态存储单元实现在CMOS /大容量
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申请号: US464099申请日: 1983-02-04
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公开(公告)号: US4499558A公开(公告)日: 1985-02-12
- 发明人: Moshe Mazin , William E. Engeler
- 申请人: Moshe Mazin , William E. Engeler
- 申请人地址: NY Schenectady
- 专利权人: General Electric Company
- 当前专利权人: General Electric Company
- 当前专利权人地址: NY Schenectady
- 主分类号: G11C11/412
- IPC分类号: G11C11/412 ; H01L27/092 ; H01L27/11 ; G11C11/40
摘要:
A five-transistor CMOS static random-access memory cell which does not require a voltage on the address line higher than the supply voltage to effect writing, and so may be fabricated employing CMOS technology on a bulk single-crystal semiconductor substrate. The cell includes a latch comprising a complementary pair of IGFETs for actively storing one binary logic state. For storing the other binary logic state, there is only a single pull-up transistor connected to one data node and a high-impedance leakage current discharge path for the other data node. The cell also includes a pair of input/output gating transistors connected to the data nodes and operating in push-pull. Various forms of high impedance leakage current discharge path are disclosed, none of which require any increase in chip area. In one form, the high-impedance current discharge path comprises an IGFET having its gate tied to its drain terminal and having a channel extending between device regions which exist on the chip in any event for other purposes. In another form, a reverse-biased PN junction diode included in one of the gating transistors has sufficient conductivity to discharge leakage current to ground.