公开(公告)号：US4901285A

公开(公告)日：1990-02-13

申请号：US316590

申请日：1989-02-27

申请人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

发明人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

IPC分类号： G11C17/12

CPC分类号： G11C17/126

摘要： An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

摘要翻译： 一种具有多条行线的集成电路存储器; 多条选择线; 多个输出线; 多个存储单元; 每对存储器单元具有耦合到所述多条输出线中的选择一条输出线的公共输出和耦合到所述多条行线中的选择一条线的公共地址输入，其中所选择的所述一对存储器单元中的存储单元的模糊性 耦合到所述多行输入行中的选择一行和所述多条输出行中的选择一行由所耦合的所述多条选择行中的两个选定行选择。 还提供了响应于输入地址以启用多条行线中的选择行的第一解码器，以及响应于行线和输入地址的第二解码器，用于启用选择线中的选择线 其对应于具有启用行行的存储器单元对。

公开(公告)号：US4506349A

公开(公告)日：1985-03-19

申请号：US451689

申请日：1982-12-20

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： G11C11/411 ,  G11C11/412 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  G11C11/40

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/108 ,  Y10S257/903

摘要： A memory cell of the general type employing one pair of IGFETs defining data nodes and cross-coupled in a latch circuit configuration for storing data, and another pair of IGFETs serving as transmission gates to selectively couple data into or out of the cell. A circuit technique provides fast writing speed by avoiding the use of load resistors in either the charge or discharge paths for the data nodes and yet ensures that the data nodes are pulled either fully to logic high or fully to logic low, as the case may be, without limitation by threshold voltage offset between the gate and source terminals of the IGFETs serving as transmission gates. High impedance leakage current discharge resistances are included, and serve only the function of discharging leakage at the nodes to maintain memory. In the disposed circuit configurations, the latch IGFETs are of opposite channel conductivity type compared to the gating IGFETs. Various alternative forms of suitable high impedance leakage current resistances are disclosed, including a resistive sea above the cell and leakage paths included within the gating IGFETs. The high impedance leakage current discharge resistances may be eliminated to provide a dynamic memory cell.

摘要翻译： 一般类型的存储单元采用定义数据节点的一对IGFET和用于存储数据的锁存电路配置的交叉耦合，以及用作传输门的另一对IGFET，用于选择性地将数据耦合到单元或从单元中耦合。 电路技术通过避免在数据节点的充电或放电路径中使用负载电阻器来提供快速的写入速度，并且确保将数据节点完全拉至逻辑高电平或完全拉至逻辑低电平（视情况而定） 而不限于用作传输门的IGFET的栅极和源极端子之间的阈值电压偏移。 包括高阻抗泄漏电流放电电阻，并且仅用于在节点处泄漏泄漏以维持存储器的功能。 在布置的电路配置中，与门控IGFET相比，锁存器IGFET具有相反的沟道导电类型。 公开了适当的高阻抗泄漏电流电阻的各种替代形式，包括在电池单元之上的电阻海和包括在门控IGFET内的泄漏路径。 可以消除高阻抗漏电放电电阻以提供动态存储单元。

公开(公告)号：US4484087A

公开(公告)日：1984-11-20

申请号：US478015

申请日：1983-03-23

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： H03K3/354 ,  H01L27/11 ,  H03K3/356 ,  H03K3/3562 ,  G11C19/28 ,  H03K19/096 ,  H03K23/22

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H03K3/356104 ,  H03K3/35625

摘要： A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node. A cross-coupled switching element comprising a second P-channel IGFET has its gate connected to the complementary data output node and is arranged to selectively connect the data storage node to the voltage supply node. A third P-channel IGFET has its channel arranged to selectively connect the data storage node to the voltage supply node when the cell is disabled. A second N-channel IGFET is arranged to selectively connect the data storage node to the data input node. A high impedance leakage current discharge path electrically connects the data storage node to the one voltage supply node, and discharges any leakage current on the data storage node. The high impedance leakage current discharge path may take a variety of forms, and need not comprise a discrete resistor.

摘要翻译： 在一个实施例中，用于静态触发器应用的五晶体管CMOS静态锁存单元包括具有数据输入节点，数据存储节点，互补数据输出节点，时钟输入节点，用于选择性地使能或 不启用电池，以及一对电源供应节点。 基本上标准的CMOS反相器具有连接到互补数据输出节点的输出。 反相器包括互补的IGFET对，即N沟道IGFET和P沟道IGFET。 N沟道反相器IGFET的通道选择性地将互补数据输出节点电连接到地。 P沟道反相器IGFET的通道选择性地将互补数据输出节点电连接到电压供应节点。 逆变器晶体管栅电极连接到数据存储节点。 包括第二P沟道IGFET的交叉耦合开关元件的栅极连接到互补数据输出节点并被布置成有选择地将数据存储节点连接到电压供应节点。 第三P沟道IGFET具有其通道，其布置成在单元被禁用时选择性地将数据存储节点连接到电压供应节点。 第二N沟道IGFET被布置成选择性地将数据存储节点连接到数据输入节点。 高阻抗泄漏电流放电路径将数据存储节点电连接到一个电压供应节点，并且在数据存储节点上放电任何漏电流。 高阻抗漏电流放电路径可以采取各种形式，并且不需要包括分立电阻器。

公开(公告)号：US4675838A

公开(公告)日：1987-06-23

申请号：US667199

申请日：1984-11-01

申请人： Moshe Mazin ,  Edward T. Lewis

发明人： Moshe Mazin ,  Edward T. Lewis

IPC分类号： G06F7/50 ,  G06F7/507 ,  G06F7/508 ,  G06F17/10

CPC分类号： G06F7/507

摘要： A multibit digital adder is shown wherein a pair of carry generating circuitries is disposed between single adders for each bit in the digital numbers to be added, each one of such carry generating circuitries being responsive to a different carry-in signal and to the level of the bits applied to the associated single bit adder to produce the proper carry-in signal to the following single bit adder.

摘要翻译： 示出了一种多位数字加法器，其中在要添加的数字数字中的每个位的单个加法器之间设置一对进位产生电路，这些进位生成电路中的每一个响应于不同的进位输入信号和 这些位应用于相关联的单位加法器，以产生适当的进位信号给以后的单位加法器。

公开(公告)号：US4599704A

公开(公告)日：1986-07-08

申请号：US567842

申请日：1984-01-03

申请人： Moshe Mazin

发明人： Moshe Mazin

IPC分类号： G11C17/12 ,  G11C17/00

CPC分类号： G11C17/12

摘要： A non-volatile integrated circuit memory is provided having an array of memory elements selectively programmable to store complimentary binary data, each one of such memory elements being formed in a different region of the integrated circuit and having an address terminal, an output terminal, a ground terminal, and a power supply terminal. Those memory cells programmed into a first logical state are provided with transistor action between the output terminal and the power supply terminal and are inhibited from having transistor action between the output terminal and the ground terminal. Conversely, those memory cells programmed to store the complementary logic state are inhibited from having transistor action between the output terminal and the power supply terminal and are provided with transistor action between the ground terminal and the output terminal. In either programmed state, the transistor action is controlled by signals fed to the address terminal of the cells. With such arrangement, since transistor action is prevented between the power supply terminal and the ground terminal of each cell, an electrical open-circuit is always present to the power supply with the result that a precharge cycle is not required during memory addressing to reduce power. The elimination of such pre-charge cycle thereby eliminates the time delays inherent with the precharge cycle circuitry to thereby increase the operating speed of the memory and, further, the elimination of the circuitry increases the storage capacity of the ROM by making more chip area available for memory cells.

摘要翻译： 提供了一种非易失性集成电路存储器，其具有可选地可编程以存储互补二进制数据的存储器元件阵列，这些存储器元件中的每一个形成在集成电路的不同区域中，并且具有地址端子，输出端子， 接地端子和电源端子。 被编程为第一逻辑状态的那些存储器单元在输出端子和电源端子之间提供晶体管作用，并且被禁止在输出端子和接地端子之间具有晶体管作用。 相反，被编程为存储互补逻辑状态的存储单元被禁止在输出端子和电源端子之间具有晶体管作用，并且在接地端子和输出端子之间提供晶体管作用。 在编程状态下，晶体管的动作由馈送到单元的地址端子的信号控制。 通过这种布置，由于在每个单元的电源端子和接地端子之间防止了晶体管的动作，电源总是存在电开路，结果是在存储器寻址期间不需要预充电循环以减少功率 。 消除这种预充电循环从而消除了预充电循环电路固有的时间延迟，从而提高存储器的工作速度，此外，电路的消除通过使更多的芯片面积可用来增加ROM的存储容量 用于记忆细胞。

公开(公告)号：US4866658A

公开(公告)日：1989-09-12

申请号：US244549

申请日：1988-09-12

申请人： Moshe Mazin ,  Dennis A. Henlin ,  Edward T. Lewis

发明人： Moshe Mazin ,  Dennis A. Henlin ,  Edward T. Lewis

IPC分类号： G06F7/50 ,  G06F7/503

CPC分类号： G06F7/503 ,  G06F2207/3876

摘要： A high speed full adder circuit is shown to include logic circuitry responsive to the levels of the two digital signals to be added for: (a) immediately producing an appropriate carry signal when the levels of the digital signals are the same; and (b) inverting the carry signal into such adder when the levels of the digital signals differ.

摘要翻译： 高速全加器电路被示为包括逻辑电路，其响应于要添加的两个数字信号的电平：（a）当数字信号的电平相同时立即产生适当的进位信号; 和（b）当数字信号的电平不同时，将进位信号转换成这样的加法器。

公开(公告)号：US4589008A

公开(公告)日：1986-05-13

申请号：US299344

申请日：1981-09-04

申请人： Roger G. Stewart ,  Moshe Mazin

发明人： Roger G. Stewart ,  Moshe Mazin

IPC分类号： G11C5/02 ,  H01L23/498 ,  H01L27/12 ,  H01L23/50

CPC分类号： H01L23/49872 ,  G11C5/025 ,  H01L27/12 ,  H01L2924/0002 ,  Y10S257/91 ,  Y10S257/926

摘要： Apparatus, comprising a series of staggered metal contacts, is used to join adjacent ends of adjacent sets of substantially parallel semiconductor lines. The lines of one set can have a conductivity type opposite that of the lines of the adjacent set. Also, one of the sets may comprise epitaxial silicon, grown on an insulating substrate such as sapphire, while the other set comprises polycrystalline silicon.

摘要翻译： 包括一系列交错的金属触点的装置用于连接相邻组的基本上平行的半导体线的相邻端。 一组的线可以具有与相邻组的线相反的导电类型。 另外，这些组中的一个可以包括在诸如蓝宝石的绝缘衬底上生长的外延硅，而另一组包括多晶硅。

公开(公告)号：US4521695A

公开(公告)日：1985-06-04

申请号：US478014

申请日：1983-03-23

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： H03K3/356 ,  G11C19/28 ,  H03K19/096 ,  H03K23/22

CPC分类号： H03K3/356104

摘要： A D-type latch circuit employing only six insulated-gate field-effect transistors and four diodes includes three CMOS inverters, the first and third of which are modified inverters capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. To accomplish this, each of the first and third inverters includes a pair of isolation diodes. Voltage supply nodes of the second inverter are connected to latch voltage supply nodes for continuously enabling the second inverter. However, the voltage supply nodes of the first and second inverters are connected to a pair of complementary clock input nodes in a manner such that, when the clock input nodes have applied thereto one set of complementary logic voltage levels for enabling the latch, the first inverter is enabled and the third inverter is disabled, and when the clock input nodes have applied thereto a complementary set of logic voltage levels for not enabling the latch, the first inverter is disabled and the third inverter is enabled. In the overall configuration, the input node of the first inverter is connected to the data input node of the overall latch, and the output node of the first inverter is connected to the complementary data output node (Q) of the overall latch, and also to the input node of the second inverter. The output node of the second inverter is connected to the latch data output node (Q) of the overall latch. Finally, the third inverter is cross-coupled with the second inverter in a latching configuration. In particular, the input of the third inverter is connected to the output of the second inverter, and the input of the second inverter is connected to the output of the third inverter.

摘要翻译： 仅使用六个绝缘栅场效应晶体管和四个二极管的D型锁存电路包括三个CMOS反相器，第一和第三反相器是根据施加的电源电压极性的感测能够选择性地使能或禁用的修改的反相器 到此。 为了实现这一点，第一和第三逆变器中的每一个包括一对隔离二极管。 第二反相器的电源节点连接到锁存电压供应节点，用于连续启用第二反相器。 然而，第一和第二反相器的电压供应节点以这样的方式连接到一对互补时钟输入节点，使得当时钟输入节点已施加一组用于使能锁存器的互补逻辑电压电平时，第一 反相器被使能，第三反相器被禁止，并且当时钟输入节点已经施加了用于不使能锁存器的互补的逻辑电压电平时，第一反相器被禁止并且第三反相器被使能。 在总体结构中，第一反相器的输入节点连接到总体锁存器的数据输入节点，第一反相器的输出节点连接到整体锁存器的互补数据输出节点（＆amp; upbar＆Q），以及 也到第二个反相器的输入节点。 第二反相器的输出节点连接到整体锁存器的锁存数据输出节点（Q）。 最后，第三个逆变器与第二个逆变器交叉耦合在锁定结构中。 特别地，第三反相器的输入连接到第二反相器的输出，第二反相器的输入连接到第三反相器的输出。

公开(公告)号：US4484088A

公开(公告)日：1984-11-20

申请号：US464098

申请日：1983-02-04

申请人： Moshe Mazin ,  William E. Engeler

发明人： Moshe Mazin ,  William E. Engeler

IPC分类号： H01L27/092 ,  H03K3/356 ,  H01L29/78

CPC分类号： H03K3/356104 ,  H01L27/092

摘要： An R/S latch circuit employing four IGFETs, one pair of P-channel IGFETs, and another pair of N-channel IGFETs. The P-channel IGFETs have channels respectively connecting Q and Q data output nodes to +V.sub.DD, and gates cross-connected to the opposite data output nodes. The N-channel IGFETs have channels respectively connecting the Q and Q data output nodes to ground, and have gates which respectively comprise the Reset (R) and Set (S) data inputs. A pair of high impedance leakage current paths may also be provided respectively electrically connecting the Q and Q data output nodes to ground. Particular integrated circuit R/S latch structures are disclosed.

摘要翻译： 采用四个IGFET，一对P沟道IGFET和另一对N沟道IGFET的R / S锁存电路。 P沟道IGFET具有分别将Q和＆Upbar＆Q数据输出节点连接到+ VDD的通道，并且与交叉连接到相对的数据输出节点的门。 N沟道IGFET具有分别将Q和＆amp; Upbar＆Q数据输出节点连接到地的通道，并具有分别包括Reset（R）和Set（S）数据输入的门。 还可以提供一对高阻抗漏电流路径，分别将Q和＆amp; Upbar＆Q数据输出节点电连接到地。 公开了特定的集成电路R / S锁存结构。

公开(公告)号：US4423432A

公开(公告)日：1983-12-27

申请号：US299791

申请日：1981-09-04

申请人： Roger G. Stewart ,  Moshe Mazin

发明人： Roger G. Stewart ,  Moshe Mazin

IPC分类号： G11C5/02 ,  G11C17/18 ,  H01L27/12 ,  G11C11/40 ,  H01L27/00

CPC分类号： H01L27/12 ,  G11C17/18 ,  G11C5/025 ,  Y10S257/926

摘要： Apparatus for decoding multiple input lines includes a line selector and a line deselector. The line selector is capable of receiving a plurality of closely spaced input lines and simultaneously decoding the input lines into at least one output line having an effective pitch which can be arbitrarily greater than the pitch of the input lines. An array of MOS transistors is formed in the line selector to decode the input lines while increasing the output pitch relative to the input pitch. Similarly, the line deselector receives the same plurality of input lines and insures that deselected lines are connected to an appropriate voltage potential in order to prevent them from "floating".

摘要翻译： 用于解码多个输入线的装置包括线路选择器和线路选择器。 线选择器能够接收多个紧密间隔的输入线，并且同时将输入线解码为具有任意大于输入线的间距的有效间距的至少一个输出线。 在线选择器中形成MOS晶体管阵列，以便在输入线路相对于输入节距增加输出线的同时解码输入线。 类似地，线路选择器接收相同的多条输入线，并确保取消选择的线路连接到适当的电压电位，以防止它们“浮动”。