发明授权
- 专利标题: Digital data processing system for executing instructions containing operation codes belonging to a plurality of operation code sets and names corresponding to name table entries
- 专利标题(中): 数字数据处理系统,用于执行包含属于多个操作码集的操作码和与名称表条目对应的名称的指令
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申请号: US266423申请日: 1981-05-22
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公开(公告)号: US4499604A公开(公告)日: 1985-02-12
- 发明人: Gerald F. Clancy , Ronald H. Gruner , Stephen I. Schleimer , Craig J. Mundie , Steven J. Wallach , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein , Richard G. Bratt
- 申请人: Gerald F. Clancy , Ronald H. Gruner , Stephen I. Schleimer , Craig J. Mundie , Steven J. Wallach , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein , Richard G. Bratt
- 申请人地址: MA Westboro
- 专利权人: Data General Corporation
- 当前专利权人: Data General Corporation
- 当前专利权人地址: MA Westboro
- 主分类号: G06F9/318
- IPC分类号: G06F9/318 ; G06F9/35 ; G06F9/30
摘要:
A digital computer system having a memory for storing and providing data including instructions and a processor for processing data in response to the instructions and providing memory operation specifiers to the memory which specify an address of a data item and the memory operation to be performed on it. The instructions in the digital computer system include operation codes belonging to more than one set of operation codes and names representing items to be processed in the operation specified by the operation code. The data in memory further includes name table entries. Each name table entry corresponds to a name and contains information specifying the address of the item represented by the name. The processor includes apparatus for decoding each operation code in response to the operation code and to a dialect value contained in the decoding apparatus which specifies which operation code set the operation code being decoded belongs to. The processor further includes apparatus for processing names by resolving them to produce the addresses specified by their corresponding name table entries and control apparatus responsive to the instruction decoding apparatus and the name processing apparatus for controlling the processor and providing memory operation specifiers containing the addresses produced by the name processing means to the memory.