公开(公告)号：US6014009A

公开(公告)日：2000-01-11

申请号：US959021

申请日：1997-10-28

申请人： Robert P. Wierzbicki ,  Paul Whitcher

发明人： Robert P. Wierzbicki ,  Paul Whitcher

IPC分类号： H01M2/10 ,  H01M10/34 ,  H02J7/00

CPC分类号： H02J7/0024 ,  H01M2/1022 ,  H01M10/345 ,  H01M2/1055

摘要： An electronic device supplied power from either a single rechargeable battery or four non-rechargeable batteries. The single rechargeable battery is preferably a 4.8 volt, DURACELL DR-121 rechargeable battery which includes a first end having positive and negative terminal contacts, a pair of recharging contacts and a key. Each of the four non-rechargeable batteries are preferably AA size, lithium batteries and are configured so that a first pair of batteries in series are in parallel with a second pair of batteries in series. The electronic device comprises a housing shaped to include a battery cavity which can accept either type of battery source. The battery cavity comprises a bottom wall, a front end wall, a back end wall and a pair of sidewalls. One of the sidewalls includes a slot which is sized and shaped to accept the key of the rechargeable battery, the slot enabling the rechargeable battery to be inserted in the battery cavity only in its proper orientation relative to the battery cavity. The electronic device also includes an electronic circuit within the housing for enabling the electronic device to perform a particular operation, the electronic circuit receiving power from the battery source by a battery circuit. The electronic device further comprises a pair of spring contacts on the front end wall, a pair of looped wire contacts mounted on the back end wall, a plurality of a plurality of flexible fingers formed in the sidewalls and plurality of flexible tabs formed on the bottom wall which all serve to maintain either battery source in an operative electrical contact position within the battery cavity.

摘要翻译： 电子设备从单个可充电电池或四个不可充电电池供电。 单个可再充电电池优选为4.8V的DURACELL DR-121可再充电电池，其包括具有正和负端子触点的第一端，一对充电触点和键。 四个不可充电电池中的每一个优选为AA尺寸的锂电池，并且被配置为使得串联的第一对电池与第二对串联的电池并联。 电子设备包括成型为包括能够接受任一类型的电池源的电池腔的壳体。 电池腔包括底壁，前端壁，后端壁和一对侧壁。 侧壁中的一个包括尺寸和形状以接受可再充电电池的键的槽，该槽使得可再充电电池仅能够相对于电池腔以适当的方向插入到电池腔中。 电子设备还包括壳体内的电子电路，用于使得电子设备能够执行特定操作，电子电路通过电池电路从电池源接收电力。 电子设备还包括前端壁上的一对弹簧触点，安装在后端壁上的一对环形线触点，形成在侧壁中的多个多个柔性指状物，以及形成在底部的多个柔性突出部 其全部用于将电池源保持在电池腔内的有效电接触位置。

公开(公告)号：US5956754A

公开(公告)日：1999-09-21

申请号：US796651

申请日：1997-03-03

申请人： Jeffrey S. Kimmel

发明人： Jeffrey S. Kimmel

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F2212/656 ,  G06F2212/682

摘要： A method for use in a multiprocessor computer system where data objects larger than the address space of a single task are mapped in main memory and the translation lookaside buffer (TLB) is maintained by user mode software is disclosed. The method uses lazy TLB updating that allows stale data to stay in the TLB until it needs to be purged.

摘要翻译： 公开了一种在多处理器计算机系统中使用的方法，其中大于单个任务的地址空间的数据对象被映射到主存储器中，并且翻译后备缓冲器（TLB）由用户模式软件维护。 该方法使用延迟TLB更新，允许过期数据保留在TLB中，直到需要清除。

公开(公告)号：US5887146A

公开(公告)日：1999-03-23

申请号：US695556

申请日：1996-08-12

申请人： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

发明人： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC分类号： G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F13/00 ,  G06F1/12

CPC分类号： G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

摘要： A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

摘要翻译： 基于硬件体系结构的非常快速，高效，高度可扩展，高效率的CCNUMA处理系统，可最大限度地减少系统总线争用，通过维护强大的排序和避免重试来最大化处理进度，并实现全映射目录结构高速缓存一致性协议。 缓存相干非均匀存储器访问（CCNUMA）架构在包括由主板和两个子板组成的多个集成模块的系统中实现。 插入主板的子板每个都包含两个作业处理器（JP），高速缓存和输入/输出（I / O）功能。 直接位于主板上的是两个小型计算机系统接口（SCSI）和一个局域网（LAN）接口形式的附加集成I / O功能。 主板包括主存储器，存储器控制器（MC）和用于高速缓存一致性的目录DRAM。 主板还包括GTL背板接口逻辑，系统时钟生成和分配逻辑，以及包括用于系统初始化的微控制器的本地资源。 交叉开关将各种逻辑块连接在一起。 一个完整的主板包含2个JP子板，2个PCI扩展板和最多512 MB的主内存。 每个子板包含两个50MHz的Motorola 88110 JP复合体，具有相关联的88410缓存控制器和1MB 2级缓存。 还提供单个16 MB的第三级直写缓存，并由第三级缓存控制器控制。

公开(公告)号：US5809256A

公开(公告)日：1998-09-15

申请号：US661504

申请日：1996-06-11

申请人： Daniel Dennis Najemy

发明人： Daniel Dennis Najemy

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081

摘要： A soft power switch for insertion and removal of a logic unit in a system during continuing operation of the system, including a current switch for each supply voltage to the logic unit that is to be protected, each current switch having a current input connected from a corresponding system power source and a current output connected to the logic unit. The switch includes a gate drive delay connected to each current switch that provides a gate signal controlling the flow of current through each current switch, and a connector having staggered connector pins for sequenced connection of power and control signals as the logic unit is inserted or withdrawn, the soft switch responding to the sequence of control and power signals by controllably and gradually increasing or decreasing the current through the current switches as the logic unit is inserted or withdrawn.

摘要翻译： 一种软电源开关，用于在系统的连续操作期间插入和移除系统中的逻辑单元，包括用于每个电源电压到待保护的逻辑单元的电流开关，每个电流开关具有从 相应的系统电源和连接到逻辑单元的电流输出。 开关包括连接到每个电流开关的栅极驱动延迟，其提供控制通过每个电流开关的电流的栅极信号，以及具有交错连接器引脚的连接器，用于在逻辑单元插入或撤回时对功率和控制信号进行顺序连接 ，软开关响应于控制和功率信号的顺序，通过随着逻辑单元的插入或取出可控地逐渐增加或减少通过电流开关的电流。

公开(公告)号：US5687089A

公开(公告)日：1997-11-11

申请号：US73069

申请日：1992-09-24

申请人： Joseph P. Deyesso

发明人： Joseph P. Deyesso

IPC分类号： G06F11/32 ,  G11B33/12 ,  G06F19/00

CPC分类号： G11B33/122 ,  G06F11/325

摘要： A drive regulator circuit board for use with a 3.50 inch disk drive unit. The drive regulator circuit board includes a regulator section for receiving +24 volts distributed power and providing therefrom regulated +5V and +12V DC power, a monitor circuit for monitoring the +5V DC and +12V DC so generated, a SCSI bus reset pulser circuit for generating a SCSI bus reset pulse upon insertion or removal of the drive module, PALS for comparing the local address with an incoming address, control and for turning the DC voltages on or off in response to certain prearranged commands as well as providing SCSI bus activity indication, and a bus for providing SCSI ID information to said 3.50 inch disk drive unit.

摘要翻译： 用于3.50英寸磁盘驱动器的驱动调节器电路板。 驱动调节器电路板包括一个调节器部分，用于接收+24伏分布式电源，并提供调节+ 5V和+ 12V直流电源，一个用于监控所产生的+ 5V直流和+ 12V直流电源的监控电路，一个SCSI总线复位脉冲发生器电路 用于在插入或移除驱动器模块时产生SCSI总线复位脉冲，PALS用于将本地地址与输入地址进行比较，控制和响应某些预先安排的命令打开或关闭直流电压，以及提供SCSI总线活动 指示和用于向所述3.50英寸磁盘驱动器单元提供SCSI ID信息的总线。

公开(公告)号：US5684973A

公开(公告)日：1997-11-04

申请号：US706175

申请日：1996-08-30

申请人： Timothy J. Sullivan ,  Cynthia J. Burns ,  Albert T. Andrade ,  Ralph C. Frangioso, Jr.

发明人： Timothy J. Sullivan ,  Cynthia J. Burns ,  Albert T. Andrade ,  Ralph C. Frangioso, Jr.

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0653 ,  G06F12/0607

摘要： An expandable memory system and a method for operating a memory system having a variable number of memory banks are described. The memory system can utilize a variable number of separately replaceable memory banks which can be implemented with memory element, such as dynamic random access memory chips, which are of differing speeds and or sizes. The memory system implements an interleaving of memory addresses among the memory banks as a function of the number of banks actually present so that successive memory accesses are not unnecessarily delayed by the recovery times of the memory elements. The memory system includes a programmable address decoder having a writable memory which provides bank address signals. Each of the banks includes a respective delay line for providing an output signal a respective presettable time after address signals are received by that bank for signalling to the host that data is ready to be transferred.

摘要翻译： 描述了可扩展存储器系统和用于操作具有可变数量的存储体的存储器系统的方法。 存储器系统可以利用可变数量的可单独替换的存储体，其可以用不同速度和/或尺寸的存储器元件（例如动态随机存取存储器芯片）来实现。 存储器系统实现存储器组之间的存储器地址的交织，作为实际存在的存储体的数量的函数，使得连续存储器访问不会被存储元件的恢复时间不必要地延迟。 存储器系统包括具有提供存储体地址信号的可写存储器的可编程地址解码器。 每个存储体包括相应的延迟线，用于在由该存储体接收到地址信号以向该主机发信号以准备传送数据之后，将输出信号提供相应的预设时间。

公开(公告)号：US5617558A

公开(公告)日：1997-04-01

申请号：US466334

申请日：1995-06-06

申请人： Michael H. Kelley

发明人： Michael H. Kelley

IPC分类号： G06F12/14 ,  G06F9/38 ,  G06F9/46 ,  G06F11/00 ,  G06F11/14 ,  G06F9/44

CPC分类号： G06F9/3824 ,  G06F11/141 ,  G06F9/3861

摘要： The time lost in unnecessarily checking for the presence of all memory references required by a special section of code in an operating system before the program is run and which dynamically protects the program requiring the memory reference from crashing if the memory reference is not presently available is substantially reduced. The method assumes that all memory references are available and begins running the special section of code. If a request is made for information not in assigned memory storage, the data processing system interrupts the running of the special section of code and undoes everything the special section of code has done prior to the interrupt. The requested memory reference is then located in storage. The information is retrieved and written into assigned memory. The special section of code is then restarted and supplied the needed information. It has been found that it takes much less time to assume the memory references will succeed and occasionally interrupt, erase and restart, than to make a time-consuming preliminary check for all memory references.

摘要翻译： 在程序运行之前，不必要地检查操作系统中的特殊代码段所需的所有存储器引用的存在的时间以及如果存储器引用当前不可用时动态保护需要存储器引用的程序崩溃的程序， 大大减少。 该方法假设所有内存引用都可用，并开始运行特殊代码段。 如果对未分配存储器存储的信息进行请求，则数据处理系统会中断特殊代码段的运行，并撤销中断前特殊部分代码的所有内容。 然后，请求的内存引用位于存储器中。 信息被检索并写入分配的存储器。 然后重新启动代码的特殊部分并提供所需的信息。 已经发现，假设存储器引用将成功并且偶尔中断，擦除和重新启动需要更少的时间，而不是对所有存储器引用进行耗时的初步检查。

公开(公告)号：US5396111A

公开(公告)日：1995-03-07

申请号：US29457

申请日：1993-03-11

申请人： Ralph C. Frangioso ,  Paul Rebello ,  Joseph M. Dunbar

发明人： Ralph C. Frangioso ,  Paul Rebello ,  Joseph M. Dunbar

IPC分类号： G06F1/10 ,  G06F1/04 ,  G06F1/12 ,  H03K5/13

CPC分类号： G06F1/04

摘要： A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals. The use of such gated clock signal generation circuitry can reduce the time needed to generate the gated clock signals from that required by previously used register PAL circuitry to improve performance of the processing system.

摘要翻译： 一种用于产生门控时钟信号的技术，用于使数据处理系统中的各种操作门控单元能够使用内部参考时钟信号来产生处理器时钟信号和门控时钟信号，使得后一个信号与 处理器时钟信号。 D-触发器电路与具有可调节时间延迟的延迟单元一起被用于产生门控时钟信号。 通过选择所需的时间延迟来适当地设置从启动电路到门控时钟信号的时间的总时间延迟，使得整个时间延迟基本上与生成处理器所需的时间延迟相同 时钟信号。 因此，门控时钟信号的边沿可以与处理器时钟信号的边缘一致。 使用这种门控时钟信号发生电路可以减少从先前使用的寄存器PAL电路所需的门控时钟信号所需的时间，以改善处理系统的性能。

公开(公告)号：US5371743A

公开(公告)日：1994-12-06

申请号：US847638

申请日：1992-03-06

申请人： Joseph P. DeYesso ,  Robert C. Solomon ,  Stephen J. Todd ,  Mark C. Lippitt

发明人： Joseph P. DeYesso ,  Robert C. Solomon ,  Stephen J. Todd ,  Mark C. Lippitt

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F11/20 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F11/006 ,  G06F13/4072 ,  G06F11/20

摘要： A method for providing on-line replacement of a module which is at a specified position in an array of modules connected to a common control processor so that all other modules in the array can continue operating during the replacement operation. When the module is removed an indication is provided to the control processor showing that removal has occurred and identifying the position thereof. When the replacement has occurred an indication thereof is provided to the control processor, the replacement module is tested, and the state of the replacement module is updated to place it in the same state it would have been in if it had not been replaced.

摘要翻译： 一种用于提供在连接到公共控制处理器的模块阵列中的指定位置处的模块的在线替换的方法，使得阵列中的所有其他模块可以在替换操作期间继续操作。 当模块被移除时，向控制处理器提供指示已经发生移除并且识别其位置的指示。 当发生替换时，将其指示提供给控制处理器，更换模块被测试，并且更新模块的状态被更新为将其置于与未被更换时相同的状态。

公开(公告)号：US5301280A

公开(公告)日：1994-04-05

申请号：US416225

申请日：1989-10-02

申请人： Philip L. Schwartz ,  Stuart Warnsman ,  Nicholas Zoda, Jr. ,  John F. Pilat

发明人： Philip L. Schwartz ,  Stuart Warnsman ,  Nicholas Zoda, Jr. ,  John F. Pilat

IPC分类号： H04L29/06 ,  G06F13/20

CPC分类号： H04L29/06

摘要： A communication protocol available to any type module on the computer bus. Application programs are treated as clients or servers. A serveport is created in the server module. A client issues a connect request to the server identifying the serveport. The server assigns a N-slot TID capability to identify, describe and protect a storage location for receiving a start buffer from the client and sends the N-slot TID to the client to establish a connection. The start buffer includes a TID list which permits the client and server to reliably communicate back and forth. Once a connection has been established, data can be moved between the server and the client. High-level instructions and commands are sent as data through these connections. After the communication has been completed, the connection can be disconnected by the client or broken by the server.

摘要翻译： 可用于计算机总线上任何类型模块的通信协议。 应用程序被视为客户端或服务器。 服务器模块中创建一个服务端口。 客户端向服务器发出连接请求，以识别服务端口。 服务器分配N时隙TID能力来识别，描述和保护用于从客户端接收起始缓冲区的存储位置，并将N时隙TID发送到客户端以建立连接。 起始缓冲器包括TID列表，其允许客户端和服务器可靠地来回通信。 建立连接后，可以在服务器和客户端之间移动数据。 高级指令和命令通过这些连接作为数据发送。 通信完成后，客户端可以断开连接，也可能被服务器破坏。