Set-Reset Master-Slave Flip-Flop circuitry uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that only signals applied to set and reset terminals which are of the appropriate state at least prior to and during the transition of a clock signal from the low to the high state cause the output terminals of the Flip-Flop to be set to or maintained in preselected levels.