发明授权
- 专利标题: NAND Logic gate circuit having improved response time
- 专利标题(中): NAND逻辑门电路具有改善的响应时间
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申请号: US377535申请日: 1982-05-12
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公开(公告)号: US4507575A公开(公告)日: 1985-03-26
- 发明人: Susumu Mori , Hideaki Yamada
- 申请人: Susumu Mori , Hideaki Yamada
- 申请人地址: JPX
- 专利权人: Nippon Electric Co., Ltd.
- 当前专利权人: Nippon Electric Co., Ltd.
- 当前专利权人地址: JPX
- 优先权: JPX56-72911 19810515
- 主分类号: H03K19/00
- IPC分类号: H03K19/00 ; H03K19/013 ; H03K19/088 ; H03K19/20 ; H03K17/04
摘要:
A NAND logic gate circuit having a first input circuit receiving a first input signal, an inverter circuit for inverting the output of the first input circuit, a second input circuit for receiving a second input signal, an AND gate circuit for producing a logical AND output signal in response to the outputs of the inverter circuit and the second input circuit, and a PNP transistor responsive to the second input signal having a low value for controlling the value of the output signal of the first input circuit independent of the value of the first input signal. The NAND gate circuit has a faster response time to changes in the value of the first input signal than comparable prior art circuits and reduces the current flow to the second input terminal when the first input signal is high and the second input signal is low.
公开/授权文献
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