公开(公告)号：US11847084B2

公开(公告)日：2023-12-19

申请号：US18328553

申请日：2023-06-02

Applicant: Apogee Semiconductor, Inc.

Inventor： Mark Hamlyn ,  David A. Grant

IPC: G06F13/40 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/013

CPC classification number: G06F13/4072 ,  H01L27/0203 ,  H01L27/092 ,  H03K19/00315 ,  H03K19/0136

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

公开(公告)号：US11726943B2

公开(公告)日：2023-08-15

申请号：US17194221

申请日：2021-03-06

Applicant: TallannQuest LLC

Inventor： Mark Hamlyn ,  David A. Grant

IPC: G06F13/40 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/013

CPC classification number: G06F13/4072 ,  H01L27/0203 ,  H01L27/092 ,  H03K19/00315 ,  H03K19/0136

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

公开(公告)号：US10250260B2

公开(公告)日：2019-04-02

申请号：US15811057

申请日：2017-11-13

Applicant: SEIKO EPSON CORPORATION

Inventor： Ryuichi Kagaya

IPC: H03K19/013 ,  H03K17/16 ,  H03K19/017

Abstract: A data communication system has a first data communication circuit for outputting a clock signal to a clock signal line, receiving data input from a data signal line, and outputting data as open drain output to the data signal line, a second data communication circuit for receiving input of a clock signal from the clock signal line, receiving input of data from the data signal line, and outputting data as open drain output to the data signal line, a first pull-up resistor connected between the data signal line and the wiring of a power supply potential, a second pull-up resistor for selectively pulling up the data signal line, and a pull-up control circuit that is connected to the second pull-up resistor, and strengthens pull-up of the data signal line at least in response to a clock signal.

公开(公告)号：US20190035455A1

公开(公告)日：2019-01-31

申请号：US15800443

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C5/14 ,  G11C11/4074 ,  H03K19/013

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US08390315B1

公开(公告)日：2013-03-05

申请号：US13354780

申请日：2012-01-20

Applicant: Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

Inventor： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

IPC: H03K19/013 ,  H03K17/16

CPC classification number: H03K19/01721 ,  H03K19/018571

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.

Abstract translation: 公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。 所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。 单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。 用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。 当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

公开(公告)号：US07514951B2

公开(公告)日：2009-04-07

申请号：US11230387

申请日：2005-09-20

Applicant: Chun Shiah

Inventor： Chun Shiah

IPC: H03K19/00 ,  H03K19/013 ,  G01R31/00 ,  G01R31/28 ,  G01N27/00 ,  G06F11/00 ,  G06F11/30 ,  G06K5/04 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC classification number: H03K19/1732

Abstract: A circuit and a method are provided to produce a noise-free multi-input I/O pad for an integrated circuit chip. The circuit includes a normal mode internal node, which connects to normal mode circuitry and a test mode internal node, which connects to test mode circuitry. There are separate transfer devices which connect the I/O pad to the normal mode circuitry and to the test mode circuitry. In addition, a third transfer device, a load device, and a new intermediate internal node are added to prevent negative input voltage swings which occur on the I/O pad during the normal mode from causing the transfer gate to the test mode circuitry from turning ON causing chip failure.

Abstract translation: 提供电路和方法来产生用于集成电路芯片的无噪声多输入I / O焊盘。 该电路包括连接到正常模式电路的正常模式内部节点和连接到测试模式电路的测试模式内部节点。 存在将I / O焊盘连接到正常模式电路和测试模式电路的单独传送装置。 此外，添加第三传送装置，负载装置和新的中间内部节点以防止在正常模式期间在I / O焊盘上发生的负输入电压摆动导致传输门到测试模式电路转动 导致芯片故障。

公开(公告)号：US6130575A

公开(公告)日：2000-10-10

申请号：US153108

申请日：1998-09-15

Applicant: Carl T. Nelson ,  Robert Essaff

Inventor： Carl T. Nelson ,  Robert Essaff

IPC: H01L27/04 ,  H01L21/822 ,  H02J1/10 ,  H02M1/00 ,  H02M1/36 ,  H02M3/155 ,  H02M3/335 ,  H03K17/00 ,  H03K17/04 ,  H03K17/042 ,  H03K17/0422 ,  H03K17/16 ,  H03K19/013 ,  G05F3/02

CPC classification number: H02M1/36 ,  H02M3/155 ,  H02M3/33507 ,  H03K17/04213 ,  H03K17/0422 ,  H02J2001/104 ,  H02M1/32 ,  H02M2001/009 ,  H03K2217/0036

Abstract: A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated circuit switching regulators operating at much lower frequencies. The circuitry provides three switch drive currents: a first (nominal) current that is provided while the switch is off in order to conserve power; a second (boosted) current, provided while the switch is transitioning from off to on in order to increase the speed at which the switching element switches on; and a third (drive) current, provided after the switch has turned on for maintaining the switch at a desired point in saturation. The drive current, additionally, varies as a function of the load on the switch in order, again, to conserve power. Additional circuitry increases the speed at which the switch turns off, by momentarily boosting base discharge current during the on-to-off transition period of the switch. The circuitry also increases speed by enabling the drive current prior to switch turn on. The circuitry can regulate both positive and negative outputs using a common error amplifier, as well as providing a multifunction node for shutdown and synchronization. Additionally, the circuitry provides improved recovery from output overshoot conditions. An improved clamp, to prevent the switch from spending too much time in a high power state (which would slow the switch down), increases the stability of the switch as compared with previously known designs.

Abstract translation: 公开了一种用于高速集成电路，双极开关调节器的驱动电路。 该电路以兆赫兹频率运行，但是如先前所提供的双极型集成电路开关稳压器的操作频率低得多。 电路提供三个开关驱动电流：在开关断开时提供的第一（标称）电流，以节省功率; 提供了当开关从断开转换到接通时提供的第二（升压）电流，以便提高开关元件接通的速度; 和第三（驱动）电流，在开关导通之后提供，以将开关保持在期望的饱和点。 此外，驱动电流根据开关上的负载而变化，以再次节省功率。 额外的电路通过在开关的接通到断开过渡期间瞬间升高基极放电电流来增加开关关断的速度。 电路还可以通过在开关导通之前启用驱动电流来提高速度。 电路可以使用公共误差放大器调节正输出和负输出，以及提供关闭和同步的多功能节点。 此外，电路提供从输出过冲条件改进的恢复。 改进的夹具，以防止开关花费太多的时间在高功率状态（这将减慢开关降低），与先前已知的设计相比，提高了开关的稳定性。

公开(公告)号：US5850158A

公开(公告)日：1998-12-15

申请号：US805346

申请日：1997-02-24

Applicant: Kevin M. Kattmann

Inventor： Kevin M. Kattmann

IPC: H03K19/00 ,  H03K19/013

CPC classification number: H03K19/0136 ,  H03K19/001

Abstract: An all npn totem pole TTL output stage is provided with an active regulation circuit that continuously senses the voltage level at the output terminal and feeds it back to control the drive signal that is applied to the base of the bottom output transistor to switch the output state of the load quickly without wasting transient current and then scale back the drive signal during steady state operation to minimize wasted current. When the load is driven into its output low state, the active regulation initially holds the drive signal at a high level so that the load switches quickly. Once the output voltage has fallen low enough, the active regulation reduces the drive signal such that the bottom output transistor is held on the edge of conduction and does not saturate. In this state, the bottom output transistor pulls the output voltage down to approximately ground without conducting any appreciable amount of current. When the load is driven back into its high state, the bottom transistor is turned off before the top output transistor is turned on. This prevents transient drive current from being drawn from the voltage supply and returned directly to ground.

Abstract translation: 所有npn图腾柱TTL输出级都配有一个有源调节电路，连续检测输出端的电压电平，并将其反馈，以控制施加到底部输出晶体管基极的驱动信号，以切换输出状态 的负载，而不浪费瞬态电流，然后在稳态运行期间缩小驱动信号，以最大限度地减少浪费的电流。 当负载被驱动到其输出低电平状态时，有源调节器最初将驱动信号保持在高电平，使得负载快速切换。 一旦输出电压下降得足够低，有源调节就会降低驱动信号，使得底部输出晶体管保持在导通边缘并且不会饱和。 在这种状态下，底部输出晶体管将输出电压降低到大约接地，而不会产生任何明显的电流。 当负载被驱动回到其高状态时，在顶部输出晶体管导通之前，底部晶体管截止。 这可以防止瞬态驱动电流从电压源中抽出并直接返回到地。

公开(公告)号：US5818259A

公开(公告)日：1998-10-06

申请号：US565695

申请日：1995-11-30

Applicant: Brian Clark Martin

Inventor： Brian Clark Martin

IPC: H03K17/04 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/0175 ,  H03K19/082

CPC classification number: H03K19/09448 ,  H03K19/013

Abstract: A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device conducts current between the input terminal of the logic device and the pull-down device when the output signal equals a certain value.

Abstract translation: 提供了具有较低驱动和低速电压的BiCMOS逻辑电路。 逻辑电路包括开关装置，其允许逻辑电路的下拉装置直接由输入信号驱动，而不必先切换MOS装置。 当输出信号等于一定值时，开关器件在逻辑器件的输入端子与下拉器件之间导通电流。

公开(公告)号：US5815015A

公开(公告)日：1998-09-29

申请号：US939310

申请日：1997-09-29

Applicant: Carl T. Nelson ,  Robert Essaff

Inventor： Carl T. Nelson ,  Robert Essaff

IPC: H01L27/04 ,  H01L21/822 ,  H02J1/10 ,  H02M1/00 ,  H02M1/36 ,  H02M3/155 ,  H02M3/335 ,  H03K17/00 ,  H03K17/04 ,  H03K17/042 ,  H03K17/0422 ,  H03K17/16 ,  H03K19/013 ,  H03L7/00

CPC classification number: H02M1/36 ,  H02M3/155 ,  H02M3/33507 ,  H03K17/04213 ,  H03K17/0422 ,  H02J2001/104 ,  H02M1/32 ,  H02M2001/009 ,  H03K2217/0036

Abstract: A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated circuit switching regulators operating at much lower frequencies. The circuitry provides three switch drive currents: a first (nominal) current that is provided while the switch is off in order to conserve power; a second (boosted) current, provided while the switch is transitioning from off to on in order to increase the speed at which the switching element switches on; and a third (drive) current, provided after the switch has turned on for maintaining the switch at a desired point in saturation. The drive current, additionally, varies as a function of the load on the switch in order, again, to conserve power. Additional circuitry increases the speed at which the switch turns off, by momentarily boosting base discharge current during the on-to-off transition period of the switch. The circuitry also increases speed by enabling the drive current prior to switch turn on. The circuitry can regulate both positive and negative outputs using a common error amplifier, as well as providing a multifunction node for shutdown and synchronization. Additionally, the circuitry provides improved recovery from output overshoot conditions. An improved clamp, to prevent the switch from spending too much time in a high power state (which would slow the switch down), increases the stability of the switch as compared with previously known designs.

Abstract translation: 公开了一种用于高速集成电路，双极开关调节器的驱动电路。 该电路以兆赫兹频率运行，但是如先前所提供的双极型集成电路开关稳压器的操作频率低得多。 电路提供三个开关驱动电流：在开关断开时提供的第一（标称）电流，以节省功率; 提供了当开关从断开转换到接通时提供的第二（升压）电流，以便提高开关元件接通的速度; 和第三（驱动）电流，在开关导通之后提供，以将开关保持在期望的饱和点。 此外，驱动电流根据开关上的负载而变化，以再次节省功率。 额外的电路通过在开关的接通到断开过渡期间瞬间升高基极放电电流来增加开关关断的速度。 电路还可以通过在开关导通之前启用驱动电流来提高速度。 电路可以使用公共误差放大器调节正输出和负输出，以及提供关闭和同步的多功能节点。 此外，电路提供从输出过冲条件改进的恢复。 改进的夹具，以防止开关花费太多的时间在高功率状态（这将减慢开关降低），与先前已知的设计相比，提高了开关的稳定性。