发明授权
- 专利标题: Horizontal scanning frequency multiplying circuit
- 专利标题(中): 水平扫描倍频电路
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申请号: US490667申请日: 1983-05-02
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公开(公告)号: US4520394A公开(公告)日: 1985-05-28
- 发明人: Kenji Kaneko
- 申请人: Kenji Kaneko
- 申请人地址: JPX Yokohama
- 专利权人: Victor Company of Japan, Ltd.
- 当前专利权人: Victor Company of Japan, Ltd.
- 当前专利权人地址: JPX Yokohama
- 优先权: JPX57-75784 19820506
- 主分类号: H04N5/93
- IPC分类号: H04N5/93 ; G11B20/10 ; G11B27/30 ; H03L7/08 ; H04N5/06 ; H04N5/10 ; H04N5/932 ; H04N5/04 ; H04N7/04
摘要:
A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with an input horizontal synchronizing signal having a horizontal scanning frequency f.sub.H of a television signal, a phase-locked-loop (PLL) for producing a signal having a frequency Nf.sub.H (N is an integer over 1), a first counter supplied with an output signal of a voltage controlled oscillator within the PLL as a clock signal, for producing a counted output every time the clock signal is counted for a predetermined counting time T1 and supplying this counted output to the flip-flop to reset the flip-flop, a second counter supplied with the output signal of the voltage controlled oscillator as a clock signal, for counting this clock signal, a counted value setting circuit for producing a high-level output according to an output of the second counter when the second counter counts for a predetermined counting time T2, where T2>T1, and an OR-gate supplied with the input horizontal synchronizing signal and an output signal of the counted value setting circuit. The OR-gate supplies its output to the flip-flop to set the flip-flop and supplies its output to the second counter to reset the second counter.
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