发明授权
- 专利标题: Semiconductor memory with delay means to reduce peak currents
- 专利标题(中): 具有延迟的半导体存储器,以减少峰值电流
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申请号: US379852申请日: 1982-05-19
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公开(公告)号: US4556961A公开(公告)日: 1985-12-03
- 发明人: Hiroshi Iwahashi , Masamichi Asano
- 申请人: Hiroshi Iwahashi , Masamichi Asano
- 申请人地址: JPX
- 专利权人: Tokyo Shibaura Denki Kabushiki Kaisha
- 当前专利权人: Tokyo Shibaura Denki Kabushiki Kaisha
- 当前专利权人地址: JPX
- 优先权: JPX56-79551 19810526; JPX56-123903 19810807
- 主分类号: G11C5/06
- IPC分类号: G11C5/06 ; G11C8/14 ; G11C11/40 ; G11C7/00
摘要:
A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.
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