发明授权
US4556961A Semiconductor memory with delay means to reduce peak currents 失效
具有延迟的半导体存储器,以减少峰值电流

Semiconductor memory with delay means to reduce peak currents
摘要:
A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.
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