发明授权
US4567581A Column decoder circuit for use with memory using multiplexed row and
column address lines
失效
列解码器电路，用于使用复用行和列地址线的存储器
- 专利标题： Column decoder circuit for use with memory using multiplexed row and column address lines
- 专利标题（中）： 列解码器电路，用于使用复用行和列地址线的存储器
-
申请号： US452156申请日： 1982-12-22
-
公开(公告)号： US4567581A公开(公告)日： 1986-01-28
- 发明人: Austin C. Dumbri , Frank J. Procyk
- 申请人： Austin C. Dumbri , Frank J. Procyk
- 申请人地址： NJ Murray Hill
- 专利权人： AT&T Bell Laboratories
- 当前专利权人： AT&T Bell Laboratories
- 当前专利权人地址： NJ Murray Hill
- 主分类号： G11C8/00
- IPC分类号： G11C8/00 ; G11C8/10 ; G11C11/40
摘要：
A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has terminated and column address information is available.
公开/授权文献
信息查询
