发明授权
- 专利标题: Semiconductor memory device having active pull-up circuits
- 专利标题(中): 具有有源上拉电路的半导体存储器件
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申请号: US561964申请日: 1983-12-15
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公开(公告)号: US4601017A公开(公告)日: 1986-07-15
- 发明人: Hirohiko Mochizuki , Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
- 申请人: Hirohiko Mochizuki , Yoshihiro Takemae , Tomio Nakano , Kimiaki Sato
- 申请人地址: JPX Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX57-223678 19821222
- 主分类号: G11C11/409
- IPC分类号: G11C11/409 ; G11C11/4094 ; G11C11/40 ; G11C7/00
摘要:
A semiconductor memory device comprises active pull-up circuits (APU.sub.1, APU.sub.2) each provided for one bit line (BL.sub.1, BL.sub.1). Each active pull-up circuit (APU.sub.1) has connections to two bit lines. That is, an active pull-up circuit (APU.sub.1) for a first bit line (BL.sub.1) comprises a first transistor (Q.sub.1) connected between a power supply terminal (V.sub.CC) and the first bit line, a second transistor (Q.sub.2) connected between the gate of the first transistor and the first bit line, and a capacitor (C.sub.1) connected to the gate of the first transistor. The gate of the second transistor is connected to a second bit line (BL.sub.1) which is paired with the first bit line. The capacitor receives an active pull-up signal (.phi..sub.AP). A circuit (Q.sub.3, Q.sub.4, Q.sub.5) is provided for transmitting a high level potential to the gate (N.sub.1) of the first transistor to precharge the capacitor.