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    Semiconductor memory device with internal control signal based upon output timing
    1.
    发明授权
    Semiconductor memory device with internal control signal based upon output timing 失效
    具有基于输出定时的内部控制信号的半导体存储器件

    公开(公告)号：US4970693A

    公开(公告)日：1990-11-13

    申请号：US484474

    申请日：1990-02-23

    申请人： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

    发明人： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

    IPC分类号： G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/40 ,  G11C11/413

    CPC分类号： G11C7/22 ,  G11C8/18

    摘要： A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

    摘要翻译： 半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。 输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。 输出电路具有连接到参考电位线的外部输出端子。 输出电路用于产生到外部输出端子的输出。 禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

    Semiconductor memory device having extended period for outputting data
    2.
    发明授权
    Semiconductor memory device having extended period for outputting data 失效
    具有用于输出数据的延长周期的半导体存储器件

    公开(公告)号：US4707811A

    公开(公告)日：1987-11-17

    申请号：US674313

    申请日：1984-11-23

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18 ,  G11C11/409

    CPC分类号： G11C8/04 ,  G11C7/1024 ,  G11C7/1033 ,  G11C8/18

    摘要： A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.

    摘要翻译： 半导体存储器件具有诸如半字节模式或页面模式的操作模式，第一地址选通信号保持在活动状态，并且第二地址选通信号在活动状态和待机状态之间被连续切换，从而使能连续的数据 输出。 在输出数据之前，根据第二地址选通信号切换到激活状态的先前输出数据被复位一次，而在输出数据之前也执行用于输出的复位操作 第一和第二地址选通信号被切换到待机状态，从而扩展数据输出的周期。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4532613A

    公开(公告)日：1985-07-30

    申请号：US356487

    申请日：1982-03-09

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Tsuyoshi Ohira

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Tsuyoshi Ohira

    IPC分类号： G11C11/407 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/40

    CPC分类号： G11C11/4093

    摘要： In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.

    摘要翻译： 在包括从存储单元阵列读出的数据信号的输出缓冲电路的半导体存储器件中，输出级MOS晶体管根据输出缓冲电路的输出信号而导通和截止，而输出缓冲器使能（OBE） 信号发生器电路，用于产生用作向输出缓冲电路的输出级的电压供给的OBE信号，提供VBS电压发生器电路，用于产生比OBE上升之前的电压源VCC高的电压VBS 信号，哪个电压VBS被用作到OBE信号发生器电路的输出级的电压供应，由此OBE信号形成为快速上升到高于电压源VCC的电平的电压波形。

    Address buffer circuit
    4.
    发明授权
    Address buffer circuit 失效
    地址缓冲电路

    公开(公告)号：US4396845A

    公开(公告)日：1983-08-02

    申请号：US243862

    申请日：1981-03-16

    申请人： Tomio Nakano

    发明人： Tomio Nakano

    IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H03K3/356 ,  H03K19/0185 ,  G11C7/00

    CPC分类号： H03K3/35606 ,  G11C11/4082 ,  G11C8/06 ,  H03K19/01855 ,  H03K3/356017

    摘要： An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-amplifier, a depletion type transistor (Q.sub.34) is used as a reference constant current source, which is independent of a power supply voltage (V.sub.DD), for the two values of the address signal of a TTL level.

    摘要翻译： 一种用于将TTL电平的地址信号（Ai）转换成MOS电平的地址信号（A）的地址缓冲器电路，其反相信号（A）包括：用于接收地址信号的前置放大器（P-AMP） 具有TTL电平; 包括触发器（FF3）的主放大器（M-AMP），用于限定触发器（FF3）的操作的电路; 以及由用于产生MOS电平的地址信号的另一个触发器（FF4）组成的输出电路（OUT）。 在前置放大器中，对于TTL电平的地址信号的两个值，耗尽型晶体管（Q34）用作参考恒流源，其与电源电压（VDD）无关。

    Tablet quickly melting in oral cavity
    6.
    发明授权
    Tablet quickly melting in oral cavity 有权
    片剂在口腔中迅速熔化

    公开(公告)号：US08580305B2

    公开(公告)日：2013-11-12

    申请号：US10542969

    申请日：2004-01-20

    申请人： Tomoharu Suga ,  Tomio Nakano

    发明人： Tomoharu Suga ,  Tomio Nakano

    IPC分类号： A61K9/42

    CPC分类号： A61K9/0056

    摘要： The object of the present invention is to provide, as a solid preparation for making it easy to take, thus improving patient's compliance etc., an intraorally rapidly disintegrating tablet which can be produced easily without any particular problem by a usual method of producing tablets with a usual tabletting machine, has practically unproblematic hardness, and disintegrate rapidly in the oral cavity. This tablet is produced by tabletting cores coated with a pharmaceutical disintegrating agent, wherein the core is a granule containing a water-soluble medicament or containing a medicament and a sugar.

    摘要翻译： 本发明的目的是提供一种易于使用的固体制剂，从而提高患者的依从性等，可以容易地制造出口服快速崩解片剂，而不会产生任何特别的问题 通常的压片机具有几乎没有问题的硬度，并且在口腔中快速分解。 该片剂通过用药物崩解剂包衣的片剂制成，其中核心是含有水溶性药物或含有药物和糖的颗粒。

    Semiconductor device having input protective function
    8.
    发明授权
    Semiconductor device having input protective function 失效
    具有输入保护功能的半导体器件

    公开(公告)号：US5747837A

    公开(公告)日：1998-05-05

    申请号：US763262

    申请日：1996-12-10

    申请人： Akihiro Iwase ,  Tomio Nakano ,  Teruo Seki

    发明人： Akihiro Iwase ,  Tomio Nakano ,  Teruo Seki

    IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/06

    CPC分类号： H01L27/0259

    摘要： A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.

    摘要翻译： 公开了一种具有扩展的输入电压推荐条件范围的半导体器件。 在实施例中，在其输入端子上具有输入保护的半导体器件包括：具有限定在半导体区域中并且分别具有第二导电类型的第一导电类型，第一和第二扩散区域的半导体区域，以及通过使用 作为基底的半导体区域，第一扩散区域作为集电极，第二扩散区域作为发射极。 第一扩散区域连接到高电位电源和低电位电源中的一个，第二扩散区域连接到输入端子，并且半导体区域连接到具有足够高的电压的另一个电源， 反向偏置半导体区域和第一扩散区域之间的结。

    Complementary semiconductor device reducing latch-up phenomenon
    9.
    发明授权
    Complementary semiconductor device reducing latch-up phenomenon 失效
    互补半导体器件减少闭锁现象

    公开(公告)号：US4862415A

    公开(公告)日：1989-08-29

    申请号：US266332

    申请日：1988-11-01

    申请人： Tomio Nakano

    发明人： Tomio Nakano

    IPC分类号： G11C11/00 ,  G05F3/20 ,  G11C5/14 ,  G11C8/10 ,  G11C11/405 ,  G11C11/407 ,  G11C11/413 ,  H01L27/00

    CPC分类号： G11C5/145 ,  G05F3/205 ,  G11C8/10

    摘要： A semiconductor device has a substrate of a first conductivity type including a well of a second conductivity type opposite to the first conductivity type. The semiconductor device comprises a bias potential generating circuit for generating a potential in the substrate or the well; a potential detecting circuit for detecting a potential of the substrate or the well and a gate circuit. The gate circuit is connected to the potential detecting circuit and to an internal circuit and applies an enable signal to the internal circuit in accordance with the detected potential of the substrate or the well. Consequently, latch-up of parasitic transistors in a CMIS-inverter circuit of the semiconductor device can be prevented.

    摘要翻译： 半导体器件具有包括与第一导电类型相反的第二导电类型的阱的第一导电类型的衬底。 半导体器件包括用于在衬底或阱中产生电位的偏置电位产生电路; 用于检测衬底或阱的电位的电位检测电路和门电路。 门电路连接到电位检测电路和内部电路，并根据检测到的衬底或阱的电位向内部电路施加使能信号。 因此，可以防止半导体器件的CMIS反相器电路中的寄生晶体管的闩锁。