Invention Grant
- Patent Title: Dual validity bit arrays
- Patent Title (中): 双有效位数组
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Application No.: US485551Application Date: 1983-04-15
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Publication No.: US4602368APublication Date: 1986-07-22
- Inventor: Joseph C. Circello , John E. Wilhite , William A. Shelly , Morgan S. Riley
- Applicant: Joseph C. Circello , John E. Wilhite , William A. Shelly , Morgan S. Riley
- Applicant Address: AZ Phoenix
- Assignee: Honeywell Information Systems Inc.
- Current Assignee: Honeywell Information Systems Inc.
- Current Assignee Address: AZ Phoenix
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F9/00
Abstract:
An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared. After all validity bits of the disabled array are reset, a clear associative memory paging (CAMP) instruction can be executed to invalidate all entries written into the associative memory by enabling the cleared disabled array and disabling the array enabled at the time such a CAMP instruction begins execution.
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