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公开(公告)号：US4602368A
公开(公告)日：1986-07-22
申请号：US485551
申请日：1983-04-15
CPC分类号： G06F12/1045
摘要： An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared. After all validity bits of the disabled array are reset, a clear associative memory paging (CAMP) instruction can be executed to invalidate all entries written into the associative memory by enabling the cleared disabled array and disabling the array enabled at the time such a CAMP instruction begins execution.
摘要翻译： 用于将虚拟字地址的虚拟页号（VPN）转换为数字计算机系统的随机存取存储器的物理字地址的物理页号（PPN）的关联存储器具有一对可独立寻址的有效性 位阵列，其中每个阵列可以在每个阵列的每个可寻址位置中存储有效位。 指针仅使一个有效位阵列接收对应于VPN的较低虚拟页号（LVPN）的地址信号。 在确定从关联存储器的相应存储器位置读出的PPN是否有效的情况下，使用从与使能的阵列的LVPN相对应的存储单元中读出的有效位。 禁用阵列的位在其被禁用之后立即被复位或清除。 在禁用阵列的所有有效位被重置之后，可以执行清除关联存储器寻呼（CAMP）指令，以通过启用清除的禁用阵列来禁用写入关联存储器的所有条目，并在此类CAMP指令时禁用启用阵列 开始执行。
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2.发明授权Method and apparatus for initiating the execution of instructions using a central pipeline execution unit 失效用于使用中央流水线执行单元发起指令执行的方法和装置
公开(公告)号：US4471432A
公开(公告)日：1984-09-11
申请号：US434196
申请日：1982-10-13
申请人： John E. Wilhite , William A. Shelly , Russell W. Guenthner , Leonard G. Trubisky , Joseph C. Circello
发明人： John E. Wilhite , William A. Shelly , Russell W. Guenthner , Leonard G. Trubisky , Joseph C. Circello
CPC分类号： G06F9/3867
摘要： A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.
摘要翻译： 一种用于启动通用数字数据处理系统的同步中央处理器单元（CPU）的指令执行的方法和中央执行流水线单元。 从CPU的指令提取单元以程序顺序获取包含地址信息和指令字段的指令。 在需要一个时钟周期的第一阶段中，使用指令的地址信息来形成有效地址的进位和和并且启动虚拟地址的形成。 同时，指令字段被解码以产生存储器命令信号和数据对准信号。 在第二阶段中，完成在第一阶段中发起的有效和虚拟地址的形成，虚拟地址的字地址部分被发送到CPU的高速缓存单元。 此外，在第二阶段期间，存储器命令信号被发送到高速缓存单元，并且指令字段被转换为多个执行单元之一的执行代码，并且指定执行代码执行代码。 在第三阶段中，将虚拟地址转换为物理地址或实际页号，该地址被发送到高速缓存单元。 执行代码被发送到指定的执行单元; 然而，如果执行单元是中央单元，则执行单元是中央单元，该单元的执行代码被转换为执行单元控制信号。 在第四阶段，将数据对准控制信号发送到中央执行流水线单元的分配器。
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公开(公告)号：US4858176A
公开(公告)日：1989-08-15
申请号：US145845
申请日：1988-01-19
申请人： John E. Wilhite , William A. Shelly
发明人： John E. Wilhite , William A. Shelly
IPC分类号： G06F9/38
CPC分类号： G06F9/3867
摘要： A distrbutor for the central execution pipeline unit of a central processor of a data processing system, which central processor has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands, are transmitted primarily from the cache unit of the central processor unit to execution units and the instruction fetch unit of the central processor unit. Some machine words are transmitted directly from the collector unit to selected units and others are transmitted after being stored in the data register of the distributor. Machine words stored in the data register can be realigned if required by an instruction by character or word alignment switches. The aligned words are then stored in the data register means prior to their being transmitted to units of the central processor. Other sources of signals transmitted by the distributor are the collector unit and registers of the distributor containing the effective address of a target word as calculated by the central execution pipeline unit, as well as copies of machine words in key registers, the A/Q registers, of certain of the execution units.
摘要翻译： 用于数据处理系统的中央处理器的中央执行流水线单元的分配器，该中央处理器具有多个执行单元。 分配器用作通信中心，机器字（诸如操作数）主要从中央处理器单元的高速缓存单元传送到中央处理器单元的执行单元和指令提取单元。 一些机器字从收集器单元直接发送到所选单元，而其他机器字被存储在分配器的数据寄存器中之后被发送。 存储在数据寄存器中的机器字可以通过字符或字对齐开关的指令进行调整。 然后将对齐的字在其被发送到中央处理器的单元之前存储在数据寄存器装置中。 由分配器发送的其他信号源是收集器单元和分配器的寄存器，其包含由中央执行流水线单元计算的目标字的有效地址，以及密钥寄存器中的机器字的副本，A / Q寄存器 ，某些执行单位。
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公开(公告)号：US4521850A
公开(公告)日：1985-06-04
申请号：US433569
申请日：1982-10-04
CPC分类号： G06F9/3804
摘要： Apparatus and method for providing an improved instruction buffer associated with a cache memory unit. The instruction buffer is utilized to transmit to the control unit of the central processing unit a requested sequence of data groups. In the current invention, the instruction buffer can store two sequences of data groups. The instruction buffer can store the data group sequence for the procedure currently in execution by the data processing unit and can simultaneously store data groups to which transfer, either conditional or unconditional, has been identified in the sequence currently being executed. In addition, the instruction buffer provides signals for use by the central processing unit defining the status of the instruction buffer.
摘要翻译： 用于提供与高速缓冲存储器单元相关联的改进的指令缓冲器的装置和方法。 指令缓冲器用于向中央处理单元的控制单元发送所请求的数据组序列。 在本发明中，指令缓冲器可以存储两个数据组序列。 指令缓冲器可以存储数据处理单元当前正在执行的过程的数据组序列，并且可以同时存储在当前执行的序列中已经被识别的有条件的或无条件的传输的数据组。 此外，指令缓冲器提供由定义指令缓冲器的状态的中央处理单元使用的信号。
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公开(公告)号：US4371927A
公开(公告)日：1983-02-01
申请号：US131739
申请日：1980-03-20
CPC分类号： G06F9/30018 , G06F12/0862 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/383 , G06F2212/6028
摘要： A data processing system includes a cache store to provide an interface with a main storage unit for a central processing unit. The central processing unit includes a microprogram control unit in addition to control circuits for establishing the sequencing of the processing unit during the execution of program instructions. Both the microprogram control unit and control circuits include means for generating pre-read commands to the cache store in conjunction with normal processing operations during the processing of certain types of instructions. In response to pre-read commands, the cache store, during predetermined points of the processing of each such instruction, fetches information which is required by such instruction at a later point in the processing thereof.
摘要翻译： 数据处理系统包括高速缓存存储器，用于向中央处理单元提供与主存储单元的接口。 中央处理单元除了用于在执行程序指令期间建立处理单元的排序的控制电路之外还包括微程序控制单元。 微程序控制单元和控制电路都包括用于在处理某些类型的指令期间结合正常处理操作来向高速缓存存储器生成预读命令的装置。 响应于预读命令，高速缓存存储器在每个这样的指令的处理的预定点期间，在其处理的稍后点获取这种指令所需的信息。
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6.发明授权Gate close failure notification for fair gating in a nonuniform memory architecture data processing system 有权门不合格故障通知，用于在不均匀的内存架构数据处理系统中进行公平门控公开(公告)号：US06480973B1
公开(公告)日：2002-11-12
申请号：US09409456
申请日：1999-09-30
IPC分类号： G06F1100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译： 在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。 对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。 在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决 试图关闭旋转门。 每个处理器检测何时在旋转门上旋转。 然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。
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7.发明授权Steering code generating apparatus for use in an input/output processing system 失效用于输入/输出处理系统的转向码产生装置
公开(公告)号：US4000487A
公开(公告)日：1976-12-28
申请号：US562362
申请日：1975-03-26
CPC分类号： G06F13/22 , G06F13/26 , G06F13/4022
摘要： An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.
摘要翻译： 输入/输出处理系统包括多个有源模块，多个无源模块，至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。 有源模块包括处理中断并执行命令序列的输入/输出处理单元和直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。 可操作地提供不同模块之间的连接的系统接口单元包括用于产生定义需要系统的另一个模块进行服务的每个模块的物理位置的转向代码的装置。 系统接口单元附加由特定模块提供的信息，产生请求请求，以产生注意力。 由系统接口单元和包括在该请求中的模块产生导向码信息确保在输入/输出处理单元在与其相关的进程运行期间执行程序期间仅对不同模块进行授权访问。
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8.发明授权Gate close balking for fair gating in a nonuniform memory architecture data processing system 有权门在非均匀的存储器架构数据处理系统中非常适合公平门控公开(公告)号：US06484272B1
公开(公告)日：2002-11-19
申请号：US09409811
申请日：1999-09-30
IPC分类号： G06F100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译： 在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。 对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。 在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决 试图关闭旋转门。 每个处理器检测何时在旋转门上旋转。 然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。
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9.发明授权公开(公告)号：US06223228B1
公开(公告)日：2001-04-24
申请号：US09156377
申请日：1998-09-17
IPC分类号： G06F112
CPC分类号： G06F9/30087 , G06F1/04 , G06F11/2236 , G06F11/3466
摘要： Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).
摘要翻译： 提供两个指令以同步数据处理系统（80）中的多个处理器（92）。 发送同步指令（TSYNC）向系统（80）中的所有活动处理器（92）发送同步处理器中断（276）。 处理器（92）通过执行等待同步（WSYNC）指令等待接收同步信号（278）。 等待这种信号（278）的每个处理器在接收到中断信号（278）之后的下一个时钟周期被激活。 提供可选的超时值以防止挂起错过中断的等待处理器（92）（278）。 每当通过接收到中断（278）激活WSYNC指令时，将启动跟踪以将固定数量的事件跟踪到内部跟踪缓存（58）。
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公开(公告)号：US4217640A
公开(公告)日：1980-08-12
申请号：US968522
申请日：1978-12-11
CPC分类号： G06F12/0855
摘要： A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing a number of blocks of information in the form of data and instructions. Directories associated with the cache store contain addresses and level control information for indicating which blocks of information reside in the cache store. The cache unit further includes control apparatus and a transit block buffer comprising a number of sections each having a plurality of locations for storing read commands and transit block addresses associated therewith. A corresponding number of valid bit storage elements are included, each of which is set to a binary ONE state when a read command and the associated transit block address are loaded into a corresponding one of the buffer locations. Comparison circuits, coupled to the transit block buffer, compare the transit block address of each outstanding read command stored in the transit block buffer section with the address of each read command or write command received from the processing unit. When there is a conflict, the comparison circuits generate an output signal which conditions the control apparatus to hold or stop further processing of the command by the cache unit and the operation of the processing unit. Holding lasts until the valid bit storage element of the location storing the outstanding read command is reset to a binary ZERO indicating that execution of the read command is completed.
摘要翻译： 数据处理系统包括耦合到耦合到主存储器的高速缓存单元的数据处理单元。 高速缓存单元包括组织成多个级别的缓存存储器，每个级别用于以数据和指令的形式存储多个信息块。 与高速缓存存储相关联的目录包含用于指示哪些信息块驻留在高速缓存存储器中的地址和级别控制信息。 高速缓存单元还包括控制装置和传输块缓冲器，其包括多个部分，每个部分具有用于存储读取命令的多个位置和与其相关联的传输块地址。 包括相应数量的有效位存储元件，当将读取命令和相关联的传输块地址加载到相应的一个缓冲器位置时，其中的每一个被设置为二进制ONE状态。 耦合到传输块缓冲器的比较电路将存储在传输块缓冲器部分中的每个未完成读取命令的传输块地址与从处理单元接收的每个读取命令或写入命令的地址进行比较。 当存在冲突时，比较电路产生输出信号，该输出信号使控制装置保持或停止高速缓存单元对命令的进一步处理和处理单元的操作。 持续持续，直到存储未完成读取命令的位置的有效位存储元件被重置为指示执行读命令的二进制零。
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