公开(公告)号：US4426680A

公开(公告)日：1984-01-17

申请号：US219809

申请日：1980-12-24

Applicant: Steven A. Tague ,  Virendra S. Negi

Inventor： Steven A. Tague ,  Virendra S. Negi

IPC: G06F7/00 ,  G06F7/76 ,  G06F9/22 ,  G06F7/38

CPC classification number: G06F9/226

Abstract: A data processing system which includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal, as well as the length and position of the most significant decimal digit in a main memory word, are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory, high order word first or low order word first, the number of double words in the operand and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor.

Abstract translation: 包括用于执行十进制字母数字指令的商业指令处理器的数据处理系统在操作数的对齐中使用只读存储器。 操作数，字符串或压缩十进制的特征以及主存储器字中最重要的十进制数字的长度和位置由数据描述符指定。 只读存储器响应于数据描述符信息以及正在执行的指令，以产生指定从主存储器读取方向字，高位字首先还是低位字首先被读取的信号， 操作数和存储在商业指令处理器的寄存器中的单词内最小或最重要的十进制数字的位置。

公开(公告)号：US4725946A

公开(公告)日：1988-02-16

申请号：US749244

申请日：1985-06-27

Applicant: Patrick E. Prange ,  James B. Geyer ,  Victor M. Morganti

Inventor： Patrick E. Prange ,  James B. Geyer ,  Victor M. Morganti

IPC: G06F9/46

CPC classification number: G06F9/52

Abstract: In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.

Abstract translation: 在具有多个处理器和过程的计算机系统中，用于与处理之间进行通信的信号量架构，以便实现进程之间的协调和协作。 本发明在固件和软件中实现，并且划分整个信号量操作的工作，使得P和V操作的简单部分（分别向进程和从进程传送和接收信号）由固件完成 ; 而P或V操作的困难工作是由软件完成的。 因此，改进的架构通过使用固件来提高系统的速度，并通过利用软件来改变功能来增加计算机系统的灵活性。

公开(公告)号：US4724431A

公开(公告)日：1988-02-09

申请号：US650941

申请日：1984-09-17

Applicant: Thomas O. Holtey ,  Kenneth E. Bruce

Inventor： Thomas O. Holtey ,  Kenneth E. Bruce

IPC: G06F3/153 ,  G09G5/02 ,  G09G5/36 ,  G09G5/377 ,  G09G5/40 ,  G09G1/16

CPC classification number: G09G5/022 ,  G09G5/026

Abstract: The invention pertains to a method and apparatus to provide for the display of characters and graphics in color. The invention includes three bit map memories which store graphics information for different colors, one character generator driven from a text memory for display of text, and an attribute memory for storing display characteristics such as inverse video and blinking. The contents of the bit map and attribute memories and the output of the character generator are used to address a pre-programmed ROM. The output from the ROM is a string of three bit words with each bit stream representing a primary color on a color CRT and being connected to the associated color input to the CRT. Composite graphics and text are displayed on the CRT.

Abstract translation: 本发明涉及一种用于提供颜色的字符和图形的显示的方法和装置。 本发明包括存储用于不同颜色的图形信息的三位图存储器，用于显示文本的文本存储器驱动的一个字符发生器，以及用于存储诸如逆视频和闪烁的显示特性的属性存储器。 位图和属性存储器的内容以及字符发生器的输出用于寻址预先编程的ROM。 来自ROM的输出是一串三位字，每个位流表示彩色CRT上的原色，并连接到与CRT相关联的颜色输入。 复合图形和文字显示在CRT上。

公开(公告)号：US4688868A

公开(公告)日：1987-08-25

申请号：US863204

申请日：1986-05-14

Applicant: Robert W. Noyes

Inventor： Robert W. Noyes

IPC: H01R13/6596 ,  H01R4/66

CPC classification number: H01R13/508 ,  H01R13/6596

Abstract: A pair of conductive ground clips each having a plurality of flexible fingers, are slid into an interference engagement with the ends of a flange of a D-shell connector. The ground clip equipped connector is held in a plastic connector housing which is latched to a conductive plate by flexible latching arms that are a part of the connector housing. As the connector housing is latched to the plate with the latching arms, flexible fingers on the clips touch the plate and flex making and maintaining a good electrical connection therewith. The ground clips maintain a proper electrical ground connection between the housing contained connector and the plate avoiding undesirable electrostatic discharge, electromagnetic interference, and radio-frequency interference.

Abstract translation: 每个具有多个柔性指状物的一对导电接地夹被滑动成与D壳连接器的凸缘的端部的干涉接合。 接地夹连接器被保持在塑料连接器壳体中，该塑料连接器壳体通过作为连接器壳体的一部分的柔性锁定臂而锁定到导电板。 当连接器壳体通过闩锁臂锁定到板上时，夹子上的柔性指状物接触板并弯曲并保持与其的良好电连接。 接地夹在保持壳体的连接器和板之间保持适当的电接地连接，避免不必要的静电放电，电磁干扰和射频干扰。

公开(公告)号：US4685032A

公开(公告)日：1987-08-04

申请号：US750441

申请日：1985-07-01

Applicant: John W. Blomstedt ,  Paul S. Yoshida ,  Wesley F. Irving ,  Vladimir Roudenko

Inventor： John W. Blomstedt ,  Paul S. Yoshida ,  Wesley F. Irving ,  Vladimir Roudenko

IPC: H01B7/00 ,  H01R4/58 ,  H05K1/02 ,  H05K1/14 ,  H05K7/00 ,  H05K7/02 ,  H05K7/14 ,  H05K7/10

CPC classification number: H05K7/1457 ,  H05K1/0263 ,  H05K1/14

Abstract: An electronic system is packaged to provide a single etched backplane. Bus bars are physically fastened to bushings which are soldered to the backplane power etch lines to provide power to the system.Printed circuit boards are plugged into connectors mounted on the backplane for receiving power and transferring logic signals between printed circuit boards. A number of power supplies are plugged into connectors mounted on the bus bars for transmitting power, and plugged into connectors for transferring logic signals.

Abstract translation: 电子系统被封装以提供单个刻蚀的背板。 母线被物理地固定到衬套上，衬套被焊接到背板电源蚀刻线以向系统供电。 印刷电路板插入安装在背板上的连接器，用于在印刷电路板之间接收电力和传送逻辑信号。 一些电源插入到安装在母线上的连接器用于传输电力，并插入到用于传送逻辑信号的连接器中。

公开(公告)号：US4683466A

公开(公告)日：1987-07-28

申请号：US681539

申请日：1984-12-14

Applicant: Thomas O. Holtey ,  Kenneth E. Bruce ,  Gary J. Goss

Inventor： Thomas O. Holtey ,  Kenneth E. Bruce ,  Gary J. Goss

IPC: G09G5/02 ,  G09G1/16 ,  G09G1/28

CPC classification number: G09G5/022

Abstract: A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.

Abstract translation: 彩色显示图形系统包括三个位图存储器，用于分别存储表示红色，绿色和蓝色颜色的位。 来自每个位图存储器的相同地址位置的位的组合显示可以是八种颜色中的任何一种的像素：黑色，蓝色，绿色，青色，红色，品红色，黄色或白色。 只读存储器（ROM）存储由红色，绿色和蓝色颜色中的每一个的四乘四个矩阵组成的十六位的图案。 16位矩阵存储在其各自的位图存储器中用于随后的彩色显示。 可以使用矩阵的组合来显示上述八种颜色的阴影和任何这些阴影的混合。

公开(公告)号：US4670835A

公开(公告)日：1987-06-02

申请号：US663096

申请日：1984-10-19

Applicant: Richard P. Kelly ,  Thomas F. Joyce

Inventor： Richard P. Kelly ,  Thomas F. Joyce

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/30

CPC classification number: G06F9/26 ,  G06F9/268 ,  G06F9/28

Abstract: Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instructions which are used by a controller in each subsystem to control the operations of same. When a special condition is detected in ones of the subsystems a trap signal is sent to the next address generator which responds by generating a microinstruction address to the subsystem that generated the trap signal. The subsystem responds to the microinstruction to read out a register, the contents of which indicate the status of processing in the subsystem including the special condition. The register contents are forwarded to the processor which tests same to determine the nature of the special condition and calls a microprogram the microinstructions of which are applied to the control store of the subsystem that generated the trap signal. The subsystem responds to the microinstructions to clear the special condition. Certain subsystems may alternately send a special condition indicating signal directly to the next address generator, rather than a trap signal, and responsive thereto the next address generator calls the required microprogram to be applied to the control store of the subsystem that generated the indicating signal.

Abstract translation: 在基于中央处理器的系统中提供中断操作的装置，其中内部子系统通过由处理器中的下一个地址生成器产生的地址进行操作，并被发送到控制与每个子系统相关联的存储器，从而读出由每个子系统中的控制器使用的固件指令 子系统控制相同的操作。 当在子系统的一个子系统中检测到特殊条件时，陷阱信号被发送到下一个地址发生器，该地址发生器通过产生产生陷波信号的子系统产生一个微指令地址来进行响应。 子系统响应微指令读出寄存器，其内容表示子系统中的处理状态，包括特殊条件。 寄存器内容被转发到处理器，其对其进行测试以确定特殊条件的性质，并且将微程序的微指令应用于产生陷波信号的子系统的控制存储器。 子系统响应微指令以清除特殊情况。 某些子系统可以将特殊条件指示信号直接发送到下一个地址发生器，而不是陷阱信号，并且响应于此，下一个地址发生器调用所要求的微程序，以将其应用于产生指示信号的子系统的控制存储器。

公开(公告)号：US4639860A

公开(公告)日：1987-01-27

申请号：US806123

申请日：1985-12-06

Applicant: Arthur Peters

Inventor： Arthur Peters

IPC: G06F11/16 ,  G06F11/22 ,  G06F12/08 ,  G06F15/16

CPC classification number: G06F12/0802 ,  G06F11/1608 ,  G06F11/22

Abstract: A minicomputer system is disclosed having a bus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling an alternate route for issuing instructions from one processor to another. The logic detects information that is not to be transferred to the I/O devices and accordingly reroutes it back to the central processor and/or subprocessors.

Abstract translation: 公开了一种具有多个处理器和/或子处理器，输入/输出（I / O）单元的总线的小型计算机系统，并且包括用于启用用于从一个处理器发出指令的另一路由的逻辑。 该逻辑检测到不传输到I / O设备的信息，并因此将其重新路由回中央处理器和/或子处理器。

公开(公告)号：USD287591S

公开(公告)日：1987-01-06

申请号：US538047

申请日：1983-09-30

Applicant: Jay A. Kaplan ,  Peter Place ,  Harold G. Wood

Designer： Jay A. Kaplan ,  Peter Place ,  Harold G. Wood

公开(公告)号：US4634203A

公开(公告)日：1987-01-06

申请号：US749243

申请日：1985-06-27

Applicant: Robert W. Noyes

Inventor： Robert W. Noyes

IPC: H01R13/627 ,  H01R13/74 ,  H01R13/639

CPC classification number: H01R13/748 ,  H01R13/627

Abstract: A novel method and apparatus for latching and locking D-type electrical connectors. In one embodiment a novel "bud-stud" is utilized to replace prior art isoblocks or prior art hexagonal nuts. The bud-stud is capable of mating with either a prior art screw-type or spring-loaded latching arm to latch and lock the electrical connectors to each other and to a bulkhead.

Abstract translation: 一种用于锁定和锁定D型电连接器的新型方法和装置。 在一个实施例中，使用新颖的“芽柱”来代替现有技术的等压线圈或现有技术的六角螺母。 芽柱能够与现有技术的螺旋型或弹簧加载的闭锁臂相配合，以将电连接器彼此锁定并锁定到隔板。