发明授权
US4641419A Fabricating an integrated circuit device having a vertical pnp transistor
失效
制造具有垂直pnp晶体管的集成电路器件
- 专利标题: Fabricating an integrated circuit device having a vertical pnp transistor
- 专利标题(中): 制造具有垂直pnp晶体管的集成电路器件
-
申请号: US712761申请日: 1985-03-18
-
公开(公告)号: US4641419A公开(公告)日: 1987-02-10
- 发明人: Satoshi Kudo
- 申请人: Satoshi Kudo
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX59-49060 19840316
- 主分类号: H01L21/331
- IPC分类号: H01L21/331 ; H01L21/74 ; H01L21/76 ; H01L21/761 ; H01L21/8228 ; H01L27/082 ; H01L29/73 ; H01L29/732 ; H01L21/265
摘要:
A process for producing semiconductor devices with a high-performance vertical pnp transistor having a high h.sub.fe and a high f.sub.T, comprising a step for forming an impurity region of a high concentration in a portion of a p-type buried layer and for increasing the concentration in a diffusion layer for isolation, a step for forming an n-type well region that reaches the p-type buried layer and that serves as a base of the vertical pnp transistor, and a step for forming an emitter of the vertical pnp transistor in a portion of said n-type well region, and for forming a collector electrode contact portion of the vertical pnp transistor, said contact portion reaching said impurity region of high concentration, by introducing p-type impurities into a portion of the p-type buried layer that serves as a portion of the collector of the vertical pnp transistor and into the p-type diffusion layer that works as an isolation layer or channel stop layer.
公开/授权文献
- US5738799A Method and materials for fabricating an ink-jet printhead 公开/授权日:1998-04-14