发明授权
- 专利标题： Planarization of dielectric layers in integrated circuits
- 专利标题（中）： 集成电路中介质层的平面化
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申请号： US815603申请日： 1986-01-02
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公开(公告)号： US4642162A公开(公告)日： 1987-02-10
- 发明人: David J. Brownell , Daniel C. Christensen , David G. Erie , Daniel Youngner
- 申请人： David J. Brownell , Daniel C. Christensen , David G. Erie , Daniel Youngner
- 申请人地址： MN Minneapolis
- 专利权人： Honeywell Inc.
- 当前专利权人： Honeywell Inc.
- 当前专利权人地址： MN Minneapolis
- 主分类号： H01L21/3105
- IPC分类号： H01L21/3105 ; H01L21/768 ; B44C1/22 ; C03B15/00
摘要：
A method is disclosed for the planarization of a semiconductor device structure by a two stage planarization process which comprises: applying a dielectric layer over a first conductive layer, spin coating an organic layer onto the first dielectric layer, etching the device in a plasma etching process to substantially remove the organic planarization layer, then etching the device in a plasma etching process which etches the exposed dielectric layer to substantially remove all of it, removing the remaining organic planarization layer, followed by the application of a second dielectric layer under bias sputter deposition conditions. The bias sputter deposition fills trenches and eliminates peaks in the remaining first dielectric layer as it builds up the second dielectric layer. The process planarizes the dielectric layer without thickness variations dependent upon conductor layer pattern density.