发明授权
- 专利标题: Digital time base corrector
- 专利标题(中): 数字时基校正器
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申请号: US721658申请日: 1985-04-10
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公开(公告)号: US4677499A公开(公告)日: 1987-06-30
- 发明人: Norihisa Shirota , Takao Yamazaki , Seiichiro Iwase
- 申请人: Norihisa Shirota , Takao Yamazaki , Seiichiro Iwase
- 申请人地址: JPX Tokyo
- 专利权人: Sony Corporation
- 当前专利权人: Sony Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX59-74205 19840413
- 主分类号: G11B20/10
- IPC分类号: G11B20/10 ; A63F7/02 ; G11B20/18 ; H03K5/00 ; H03K5/13 ; H04N5/92 ; H04N5/95 ; H03K5/14
摘要:
There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.
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