发明授权
US4688193A Bit processing utilizing a row and column ladder sequence 失效
利用行和列梯形图序列进行位处理

Bit processing utilizing a row and column ladder sequence
摘要:
A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.
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