发明授权
US4691189A Comparator with cascaded latches 失效
具有级联锁存器的比较器

Comparator with cascaded latches
摘要:
In a comparator circuit, first and second latchable circuits are connected in cascade between the output of an amplifying stage and the input of a decoder to enable the comparator to operate at significantly higher frequencies with lower error levels. An input signal, to be sampled, and a reference signal are applied to the input of the amplifying stage and a "sampled" signal indicative of the difference between the input and the reference is produced at the output of the amplifying stage. The "sampled" signal produced at the output of the amplifying stage is first processed, via the first latchable circuit operated in a regenerative mode to enhance the signal, during one time interval. The enhanced signal is then processed via the second latchable circuit operated in a regenerative mode tending to further enhance the signal, during a second, succeeding, time interval, for application to the decoder.
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