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公开(公告)号：US4507649A
公开(公告)日：1985-03-26
申请号：US381732
申请日：1982-05-24
IPC分类号： H03M1/36 , H03M1/00 , H03K13/02 , H03K13/175
摘要： A flash analog-to-digital converter includes 2.sup.N comparator circuits for an N bit resolution. Each comparator comprises a summing capacitor which is alternately connected to a reference ladder and to the input signal. The majority of the capacitors are substantially charged and discharged between input potential and reference potential each cycle. The charging/discharging tends to load both the reference ladder and the input signal source. The loading is reduced by including a D.C. biased FET between the input signal source and each summing capacitor. The FET's are biased to condition them to operate as source-followers with the summing capacitors as the load element for at least a portion of the input signal range. Respective ones of the summing capacitors are thereby precluded from charging/discharging over the full input signal excursion which in turn reduces loading on associated circuitry.
摘要翻译： 闪存模数转换器包括用于N位分辨率的2N比较器电路。 每个比较器包括交替连接到参考梯形图和输入信号的求和电容器。 大多数电容器在每个周期的输入电位和参考电位之间基本充电并放电。 充电/放电倾向于加载参考电梯和输入信号源。 通过在输入信号源和每个求和电容器之间包括直流偏置FET来减小负载。 FET被偏置以使其作为源极跟随器作为源极跟随器，其中加法电容器作为输入信号范围的至少一部分的负载元件。 相应的相加电容器因此被排除在完整输入信号偏移之上进行充电/放电，这进而减小了相关电路上的负载。
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公开(公告)号：US4449118A
公开(公告)日：1984-05-15
申请号：US326153
申请日：1981-11-30
IPC分类号： H03M1/36 , H03M1/00 , H03K13/02 , H03K13/175
CPC分类号： H03M1/361
摘要： A flash type A/D converter has a plurality of transistor switch means for alternately connecting respective ones of a plurality of reference potentials or input signal to a plurality of summing capacitors each serially connected to a self biased inverter (comparator) circuit. Certain ones of the switches are configured to operate in the source follower mode to preclude excessive capacitor discharging when extremes of input signal are applied. This reduces the current required to recharge the capacitors by the reference potential source and tends to limit loading affects on the reference source. In addition certain ones of the switch transistors have their turn on or threshold potentials tailored to effectively reduce feedthrough between the respective switch control electrodes and the capacitor-switch interconnection.
摘要翻译： 闪存型A / D转换器具有多个晶体管开关装置，用于将多个参考电位或输入信号中的各个参考电位或输入信号交替地连接到多个与自偏压逆变器（比较器）电路串联连接的求和电容器。 某些开关被配置为在源极跟随器模式下操作，以防止在施加极端输入信号时电容放电过度。 这减少了由参考电位源对电容器充电所需的电流，并且倾向于限制对参考源的负载影响。 此外，某些开关晶体管的导通或阈值电位被定制以有效地减少各个开关控制电极和电容器 - 开关互连之间的馈通。
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公开(公告)号：US5036219A
公开(公告)日：1991-07-30
申请号：US359176
申请日：1989-05-31
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： A precise, high speed CMOS track (sample)/hold circuit uses a first circuit leg including four Schottky barrier diodes configured to form a Wheatstone bridge, a second leg with a single n-channel MOS transistor, an essentially constant current source having MOS transistors, a capacitor for holding output signal, and reverse biasing circuitry having MOS transistors for selectively reverse biasing the four diodes. An analog input signal is applied to the cathode of the first diode and to the anode of the second diode. An output signal of the same magnitude and polarity as the input signal is generated at an output terminal (the cathode of the third diode and the anode of the fourth diode) of the circuit when current flows through the first circuit leg. When the current flowing through the first circuit leg is switched to the second circuit leg, the capacitor, which is connected to an output terminal of the circuitry, holds the generated output signal level and the reverse biasing circuitry reverse biases all of the diodes so as to isolate the capacitor from all other components of the circuit.
摘要翻译： 精确的高速CMOS轨迹（采样）/保持电路使用包括配置为形成惠斯通电桥的四个肖特基势垒二极管的第一电路支路，具有单个n沟道MOS晶体管的第二支路，具有MOS晶体管的基本上恒定的电流源 ，用于保持输出信号的电容器和具有用于选择性地反向偏置四个二极管的MOS晶体管的反向偏置电路。 模拟输入信号施加到第一二极管的阴极和第二二极管的阳极。 当电流流过第一电路支路时，在电路的输出端子（第三二极管的阴极和第四二极管的阳极）产生与输入信号相同大小和极性的输出信号。 当流过第一电路支路的电流被切换到第二电路支路时，连接到电路的输出端子的电容器保持所产生的输出信号电平，反向偏置电路反向偏置所有二极管，以便 以将电容器与电路的所有其他组件隔离。
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公开(公告)号：US4691189A
公开(公告)日：1987-09-01
申请号：US866317
申请日：1986-05-23
摘要： In a comparator circuit, first and second latchable circuits are connected in cascade between the output of an amplifying stage and the input of a decoder to enable the comparator to operate at significantly higher frequencies with lower error levels. An input signal, to be sampled, and a reference signal are applied to the input of the amplifying stage and a "sampled" signal indicative of the difference between the input and the reference is produced at the output of the amplifying stage. The "sampled" signal produced at the output of the amplifying stage is first processed, via the first latchable circuit operated in a regenerative mode to enhance the signal, during one time interval. The enhanced signal is then processed via the second latchable circuit operated in a regenerative mode tending to further enhance the signal, during a second, succeeding, time interval, for application to the decoder.
摘要翻译： 在比较器电路中，第一和第二可锁定电路级联连接在放大级的输出端和解码器的输入端之间，以使比较器能够在具有较低误差级别的显着更高的频率下工作。 要被采样的输入信号和参考信号被施加到放大级的输入，并且在放大级的输出端产生指示输入和参考之间的差的“采样”信号。 在放大级的输出处产生的“采样”信号首先通过在再生模式下操作的第一可锁定电路被处理，以在一个时间间隔期间增强信号。 然后，通过以再生模式操作的第二可锁定电路处理增强的信号，以便在第二个后续的时间间隔期间进一步增强信号以供应用于解码器。
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公开(公告)号：US4612531A
公开(公告)日：1986-09-16
申请号：US700866
申请日：1985-02-12
摘要： In an A/D converter, a resistive network for producing 2.sup.n different voltage steps. The resistive network includes a coarse relatively high impedance resistive string which is subdivided into 2.sup.x coarse segments. The resistive network also includes a fine relatively high impedance resistive network comprised of a fine resistive element per coarse segment. Each fine resistive element is then subdivided into 2.sup.(n-x) fine sub-segments. In determining the value of an input voltage being sensed, all the coarse segments are used to sense which coarse segments brackets the input voltage. However, only the fine segment in parallel with the "bracketing" coarse resistor is then coupled to comparator means to sense which fine sub-segment brackets the input voltage.
摘要翻译： 在A / D转换器中，用于产生2n个不同电压阶跃的电阻网络。 电阻网络包括粗略的相对高阻抗的电阻串，其被细分成两个粗的段。 电阻网络还包括一个精细的相对较高阻抗的电阻网络，每个粗细段都由精细的电阻元件组成。 然后将每个精细电阻元件细分为2（n-x）个细小分段。 在确定正在感测的输入电压的值时，所有粗略的部分用于感测哪些粗略部分支配输入电压。 然而，只有与“包围”粗电阻并联的精细分段然后被耦合到比较器装置以感测哪个精细子分段支架输入电压。
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6.发明授权Apparatus for matching FET switches as for a video digital-to-analog converter 失效用于匹配视频数/模转换器的FET开关的装置
公开(公告)号：US4553132A
公开(公告)日：1985-11-12
申请号：US460656
申请日：1983-01-24
IPC分类号： H03M1/74 , H03K17/693 , H03M1/00 , H03M1/78
CPC分类号： H03K17/693 , H03M1/0604 , H03M1/785
摘要： A digital-to-analog converter includes a plurality of pairs of complementary conductivity field-effect transistors (FETs) coupled for applying reference potentials to a resistive ladder network in response to the bit values of an input digital word. A variable voltage generator develops gate biasing voltage for the FETs of one conductivity. The biasing voltage has a magnitude controlled in response to a bridge circuit including a further pair of complementary conductivity FETs also coupled to the reference potentials. As a result, the complementary conductivity FETs are automatically caused to exhibit matched conductivity characteristics.
摘要翻译： 数模转换器包括多对互补导电场效应晶体管（FET），用于响应于输入数字字的位值而将参考电势施加到电阻梯形网络。 可变电压发生器为一个电导率的FET产生栅极偏置电压。 偏置电压具有响应于包括还耦合到参考电位的另一对互补导电FET的桥接电路而受控的幅度。 结果，互补电导率FET自动产生匹配的导电特性。
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7.发明授权Analog to digital converter with integral linearity error compensation and method of operation 失效具有积分线性误差补偿和运算方法的模数转换器
公开(公告)号：US4924225A
公开(公告)日：1990-05-08
申请号：US149514
申请日：1988-01-28
CPC分类号： H03M1/0612 , H03M1/365
摘要： Integral linearity error in the operating characteristics of an analog to digital converter employing sampling comparators is reduced by recurrently connecting at least one resistive shunt across a predetermined central portion of a reference voltage divider input to the comparators. The shunt resistance is approximately an order of magnitude larger than the resistance of the shunted part of the divider. Each recurrent connection interval is of fixed duration independent of sampling rate, and each interval spans the beginning of a recurrent time of connection of said divider to said comparators.
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公开(公告)号：US4594560A
公开(公告)日：1986-06-10
申请号：US724245
申请日：1985-04-17
CPC分类号： H03F1/303
摘要： An amplifying stage and a biasing stage for the amplifying stage, each include the same number and same types of IGFETs. The biasing stage components are interconnected to produce a control voltage which is a function of its components while being responsive to a reference level setting input voltage. The control voltage is applied to the amplifying stage which, when auto-zero'ed, functions as a voltage follower producing a voltage, at its input and output, which is substantially equal to the reference level applied to the biasing stage.
摘要翻译： 用于放大级的放大级和偏置级各自包括相同数量和相同类型的IGFET。 偏置级组件互连以产生控制电压，该控制电压是其组件的函数，同时响应于参考电平设置输入电压。 控制电压被施加到放大级，在自动归零时，其作为电压跟随器在其输入和输出端处产生电压，该电压基本上等于施加到偏置级的参考电平。
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公开(公告)号：US6135355A
公开(公告)日：2000-10-24
申请号：US434959
申请日：1999-11-05
申请人： Wenyu Han , Victor Zazzu
发明人： Wenyu Han , Victor Zazzu
CPC分类号： G06K19/07716 , G06K17/00 , G06K19/10 , G06K19/18
摘要： To impede the counterfeiting of a valuable instrument (e.g., a cash card, negotiable instrument or any document), an issuance mark is formed on the instrument at a programmed distance from a reference mark located on the instrument. The information pertaining to the distance is encoded and written onto a storage medium located in the instrument. In a particular system embodying the invention, a card vending machine is programmed to encode cards with various parameters, such as the distance between the reference and issuance marks, by writing the parametric information into an information storage medium located in the card. As a corollary, in a particular system embodying the invention, a dispensing machine is programmed to read the information stored in the information storage medium and the parametric information present in the card and to then compare the stored information with the values of the actual parameters present in the card.
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公开(公告)号：US07744130B2
公开(公告)日：2010-06-29
申请号：US11803387
申请日：2007-05-14
申请人： Victor Zazzu , Wenyu Han
发明人： Victor Zazzu , Wenyu Han
CPC分类号： G06K19/14 , G06K7/12 , G06K19/06009 , G06K19/16 , G06K19/18 , Y02P90/265 , Y10S283/901
摘要： A tag with features to enable its authenticity to be determined includes a hidden code intermixed with a visible pattern such that the hidden code is not readily detectable under ambient light condition, without the use of a specially designed reader. In one embodiment the tag is formed with a first layer containing a hidden code, formed of reflective elements, which overlies a second layer which is designed to absorb light having a predetermined wavelength (e.g., IR light). The hidden code can be detected by projecting a light source having the predetermined wavelength (e.g., an IR source) at a predetermined angle on the tag and using a sensor to sense the reflection from the tag.
摘要翻译： 具有能够确定其真实性的特征的标签包括与可见图案混合的隐藏代码，使得隐藏代码在环境光条件下不容易检测，而不使用专门设计的读取器。 在一个实施例中，标签形成有包含由反射元件形成的隐藏码的第一层，该反射元件覆盖设计成吸收具有预定波长的光（例如，IR光）的第二层。 可以通过将具有预定波长的光源（例如，IR源）以预定角度投射到标签上并使用传感器来感测来自标签的反射来检测隐藏代码。
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