A multi-terminal transistor circuit structure is described for TTL applications including current sinking and "pull-down" transistor circuit elements. A transistor pair is coupled with the emitter of the second transistor coupled to the base of the first transistor. The collector and emitter of the first transistor provide first and second terminals and the bases of the transistor pair provide independent third and fourth terminals or current controlled inputs. The new circuit structure is incorporated in a tranistor transistor logic (TTL) output buffer circuit and provides first and second pull-down transistor elements having the emitter of the second transistor coupled to the base of the first pull-down transistor. An independent base drive is coupled to the base of the second pull-down transistor element. The second stage pull-down transistor element introduces full square law enhancement of .beta..sup.2 amplification of the output sinking current in a high current sinking mode while eliminating prior art feedback diodes and dual phase splitter transistors. The separate input and base drive coupling to the base of the additional pull-down avoids "current hogging" of the base drive by the phase splitter transistor. The circuit is applicable in both TTL bistate and tristate devices and is characterized by low power dissipation, low output impedance and high current sinking capability.