A video control section for a data processing system for controlling a CRT display is disclosed. The video control section includes a video memory comprising an array of dual port RAMS which is connected through an interface to the system memory bus, a shifter, a palette, a D/A converter, an oscillator section, a timing and synchronizer section and a microprocessor. The microprocessor, which is connected to the system memory bus through an interface, manages the overall operations of the video control section to generate video signals for the CRT display and in addition along with the oscillator section and timing and synchronizer section generates all of the video timing and control signals for the CRT display.