发明授权
- 专利标题: Integrated circuit having latch circuit with multiplexer selection function
- 专利标题(中): 集成电路具有多路选择功能的锁存电路
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申请号: US864466申请日: 1986-05-19
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公开(公告)号: US4709173A公开(公告)日: 1987-11-24
- 发明人: Yoshito Nishimichi , Masaru Uya , Katsuyuki Kaneko
- 申请人: Yoshito Nishimichi , Masaru Uya , Katsuyuki Kaneko
- 申请人地址: JPX Kadoma
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Kadoma
- 优先权: JPX60-105041 19860517
- 主分类号: H03K3/037
- IPC分类号: H03K3/037 ; H03K3/012 ; H03K3/356 ; H03K17/00 ; H03K19/094
摘要:
An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.
公开/授权文献
- US4173049A Flotation liner waterbed structure 公开/授权日:1979-11-06