公开(公告)号：US4779234A

公开(公告)日：1988-10-18

申请号：US866963

申请日：1986-05-27

申请人： Katsuyuki Kaneko ,  Masaru Uya ,  Yoshito Nishimichi

发明人： Katsuyuki Kaneko ,  Masaru Uya ,  Yoshito Nishimichi

IPC分类号： G11C7/00 ,  G06F5/10 ,  G06F5/12 ,  G11C8/16 ,  G11C11/41

CPC分类号： G06F5/12 ,  G11C8/16 ,  G06F2205/123

摘要： A FIFO memory using one of the ports of a RAM having two or more ports for writing and another port for reading is disclosed. Writing into the FIFO memory is done instantly, while reading from the FIFO memory is effected by holding the output of the preliminarily accessed RAM until the end of a reading operation. The output of the RAM is updated by a request from outside and according to the state of the FIFO memory, and this operation is done simultaneously with reading or writing.

摘要翻译： 公开了一种FIFO存储器，其使用具有用于写入的两个或更多个端口的RAM的端口之一和用于读取的另一个端口。 通过保持预先访问的RAM的输出直到读取操作结束来实现从FIFO存储器的读取来实现对FIFO存储器的写入。 通过来自外部的请求和根据FIFO存储器的状态来更新RAM的输出，并且该操作与读取或写入同时进行。

公开(公告)号：US4709173A

公开(公告)日：1987-11-24

申请号：US864466

申请日：1986-05-19

申请人： Yoshito Nishimichi ,  Masaru Uya ,  Katsuyuki Kaneko

发明人： Yoshito Nishimichi ,  Masaru Uya ,  Katsuyuki Kaneko

IPC分类号： H03K3/037 ,  H03K3/012 ,  H03K3/356 ,  H03K17/00 ,  H03K19/094

CPC分类号： H03K3/356052 ,  H03K17/00 ,  H03K3/012 ,  H03K3/356017

摘要： An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.

摘要翻译： 具有具有选择功能的锁存电路的集成电路包括具有多个逻辑电路的选择电路，每个逻辑电路能够根据提供的选择信号呈现三种输出状态;锁存电路，具有由第一和第二逻辑反相 电路，以及用于将选择电路的输出提供给锁存电路的输入的连接系统。 第二逻辑反相电路的输出电阻被设定为构成选择电路的逻辑电路中的任何一个的输出电阻的十倍以上。

公开(公告)号：US4601007A

公开(公告)日：1986-07-15

申请号：US573718

申请日：1984-01-25

申请人： Masaru Uya ,  Katsuyuki Kaneko

发明人： Masaru Uya ,  Katsuyuki Kaneko

IPC分类号： G06F7/50 ,  G06F7/501 ,  G06F7/503 ,  G06F7/507

CPC分类号： G06F7/5016

摘要： A full adder is constituted with complementary MOS FETs, wherein delay time of adding time and carry signal delay time are shortened as a result of reduced number of stages of signal processing gates.

摘要翻译： 全加法器由互补MOS FET构成，其中由于信号处理门的级数减少，相加时间和进位信号延迟时间的延迟时间被缩短。

公开(公告)号：US20110182846A1

公开(公告)日：2011-07-28

申请号：US12672916

申请日：2005-08-07

申请人： Tomoko Ikeda ,  Yasunari Nakama ,  Katsuyuki Kaneko ,  Shuji Nishihama ,  Tomohiro Iimura ,  Tadashi Okawa

发明人： Tomoko Ikeda ,  Yasunari Nakama ,  Katsuyuki Kaneko ,  Shuji Nishihama ,  Tomohiro Iimura ,  Tadashi Okawa

IPC分类号： A61K8/58 ,  C07F7/18 ,  A61Q1/00

CPC分类号： C09C3/12 ,  A61K8/11 ,  A61K8/27 ,  A61K8/585 ,  A61K2800/412 ,  A61Q1/02 ,  A61Q1/12 ,  C09C1/021 ,  C09C1/28 ,  C09C1/3081 ,  C09C1/3684 ,  C09C1/40 ,  C09C1/42

摘要： The present invention provides a surface treating agent that can improve texture in use and impart excellent water resistance and sebum resistance. A surface treating agent comprising an organosiloxane derivative having a divalent or trivalent metal salt of a terminal carboxyl group, represented by the following formula (1) or (3).

摘要翻译： 本发明提供一种表面处理剂，其可以改善使用中的质地并赋予优异的耐水性和耐皮脂性。 一种表面处理剂，其含有具有下述通式（1）或（3）表示的末端羧基的二价或三价金属盐的有机硅氧烷衍生物。

公开(公告)号：US06891163B2

公开(公告)日：2005-05-10

申请号：US10148829

申请日：2000-12-06

申请人： Katsuyuki Kaneko ,  Hiroshi Tsutsui ,  Shinichi Nakahara ,  Yasuhiko Shinkaji

发明人： Katsuyuki Kaneko ,  Hiroshi Tsutsui ,  Shinichi Nakahara ,  Yasuhiko Shinkaji

IPC分类号： H04N5/32 ,  H04N5/374 ,  G01T1/24 ,  H01L31/08

CPC分类号： H01L27/14659 ,  H04N5/32 ,  H04N5/374

摘要： In order to prevent destruction of a read gate by excessive storage of charge without any addition or change to the manufacturing process, the array type X-ray detection apparatus using a direct conversion system, which directly converts irradiation X-rays to charge, provides each pixel cell with a sensor section for converting X-rays to an amount of charge according to the amount of X-rays, a charge collecting electrode for storing the charge generated, a read gate for transferring the stored charge to an external read amplifier and a MIS diode using a TFT. A clamp signal is applied to one end of the MIS diode. The read gate and MIS diode are formed in the same manufacturing process. Since the amount of charge stored in the charge collecting electrode is clamped to the amount of charge corresponding to the clamp signal voltage by the MIS diode, the read gate is not destroyed even with excessive X-ray irradiation. Furthermore, instead of the MIS diode, a cutoff voltage control circuit and a cutoff gate using a TFT connected to the cutoff voltage control circuit are provided. When the output of the charge storage capacitor exceeds a cutoff voltage, the cutoff gate interrupts the inflow of charge to the charge storage capacitor to suppress further increase of output, thus preventing the read gate from being destroyed.

摘要翻译： 为了通过过量的电荷储存来防止读取门的破坏，而不会对制造过程产生任何的添加或改变，使用将照射X射线直接转换成电荷的直接转换系统的阵列型X射线检测装置， 像素单元，其具有用于根据X射线量将X射线转换成电荷量的传感器部分，用于存储产生的电荷的电荷收集电极，用于将存储的电荷传送到外部读取放大器的读取栅极和 使用TFT的MIS二极管。 钳位信号施加到MIS二极管的一端。 读栅极和MIS二极管在相同的制造工艺中形成。 由于存储在电荷收集电极中的电荷量被钳位到由MIS二极管对应于钳位信号电压的电荷量，所以即使用过量的X射线照射，读门也不会被破坏。 此外，代替MIS二极管，提供使用连接到截止电压控制电路的TFT的截止电压控制电路和截止门。 当电荷存储电容器的输出超过截止电压时，截止栅极中断电荷向电荷存储电容器的流入，以抑制输出的进一步增加，从而防止读闸门被破坏。

公开(公告)号：US5745709A

公开(公告)日：1998-04-28

申请号：US497864

申请日：1995-07-03

申请人： Ichiro Okabayashi ,  Katsuyuki Kaneko ,  Hiroshi Kadota

发明人： Ichiro Okabayashi ,  Katsuyuki Kaneko ,  Hiroshi Kadota

IPC分类号： G06F15/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F15/17375 ,  G06F13/4022

摘要： A data transfer apparatus for providing efficient data transfer between one memory device and multiple devices by providing high speed switching of the multiple devices according to a count of the number of the data transfers performed between the one memory device and any of the multiple devices. The data transfer apparatus comprises a transferring unit for controlling a data transfer between the memory and a device; a counting unit for counting one each time data is transferred; and a selecting unit for selecting a device in accordance with a count value by decoding the count value output from the counting unit. The transferring unit controls the data transfer between the memory and the device selected by the selecting unit. The above data transfer apparatus may include the counting unit consisting of n-bits of a binary counter, 2.sup.n devices, and the selecting unit consisting of a decoder that inputs n-bits and outputs 2.sup.n -bits of data.

摘要翻译： 一种数据传送装置，用于通过根据在一个存储装置与多个装置中的任一个之间执行的数据传送的次数的计数，提供多个装置的高速切换，从而在一个存储装置与多个装置之间提供有效的数据传送。 数据传送装置包括用于控制存储器和装置之间的数据传送的传送单元; 计数单元，每次数据传送一次; 以及选择单元，用于通过解码从计数单元输出的计数值来根据计数值来选择设备。 传送单元控制由选择单元选择的存储器和设备之间的数据传输。 上述数据传送装置可以包括由二进制计数器的n位组成的计数单元，2n个装置，以及由输入n位并输出2n位数据的解码器组成的选择单元。

公开(公告)号：US5838825A

公开(公告)日：1998-11-17

申请号：US784709

申请日：1997-01-16

申请人： Yoshimasa Obayashi ,  Katsuyuki Kaneko ,  Yoshiteru Mino ,  Sadafumi Tomida

发明人： Yoshimasa Obayashi ,  Katsuyuki Kaneko ,  Yoshiteru Mino ,  Sadafumi Tomida

IPC分类号： G06T9/00 ,  G06K9/36 ,  G06K9/46

CPC分类号： G06T9/007

摘要： One block of non-zero coefficients obtained through the decoding of the entropy decoding unit 2024 is stored in the coefficient storage unit 121 in accordance with positional coordinates calculated by the non-zero coefficient scanning order calculation unit 2023a and the non-zero coefficient position conversion unit 2023b. The stored non-zero coefficients are then inverse quantized by the inverse quantization unit 2022. The non-zero coefficient range calculation unit 122 specifies a region of the coefficient storage unit 121 in which the non-zero coefficients are stored. The calculation order control unit 123 controls the inverse DCT unit 2021 to only perform an inverse DCT (discrete cosine transform) for non-zero coefficients located in the specified region.

摘要翻译： 通过熵解码单元2024的解码获得的一个非零系数块根据由非零系数扫描顺序计算单元2023a计算的位置坐标和非零系数位置转换而被存储在系数存储单元121中 单位2023b。 存储的非零系数然后由逆量化单元2022进行逆量化。非零系数范围计算单元122指定存储非零系数的系数存储单元121的区域。 计算顺序控制单元123控制逆DCT单元2021仅对位于指定区域中的非零系数执行逆DCT（离散余弦变换）。

公开(公告)号：US5701509A

公开(公告)日：1997-12-23

申请号：US783178

申请日：1997-01-15

申请人： Katsuyuki Kaneko

发明人： Katsuyuki Kaneko

IPC分类号： G06F15/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F9/28 ,  G06F13/42

CPC分类号： G06F15/17381 ,  G06F13/4022

摘要： In each processing device of a parallel processor system, a processor outputs a signal when all the transmit data are transmitted to a router. A latch receives the signal from the processor to output a signal set to HIGH. To an AND gate are inputted the signal set to HIGH outputted from the latch and a signal set to HIGH which indicates that the router has no receive data received from a network. The parallel processor system performs AND operation on the outputs of the AND gates of all the processing devices, and detects that a data transmit/receive processing is completed among all the processing devices according to the results of AND operation.

摘要翻译： 在并行处理器系统的每个处理装置中，当所有发送数据被发送到路由器时，处理器输出信号。 锁存器从处理器接收信号以输出设置为高的信号。 向AND门输入从锁存器输出的高电平信号，并将信号设置为HIGH，这表示路由器没有从网络接收的接收数据。 并行处理器系统对所有处理装置的与门的输出进行AND运算，根据AND运算结果检测所有处理装置之间的数据发送/接收处理是否完成。

公开(公告)号：US5530955A

公开(公告)日：1996-06-25

申请号：US308527

申请日：1994-09-19

申请人： Katsuyuki Kaneko

发明人： Katsuyuki Kaneko

IPC分类号： G06F12/08 ,  G06F13/16 ,  G11C7/10 ,  G06F12/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1021 ,  G06F12/08 ,  G06F13/1663

摘要： A plurality of data latch circuits each used to store row data for one page from a memory cell array are provided, each data latch circuit being allotted to a data processor. An address is given in a multiplexed manner of a row address RA and a column address CA. Data in each data latch circuit is updated when the row address RA is given while the data latch circuit is selected.

摘要翻译： 提供了各自用于从存储单元阵列存储一页的行数据的多个数据锁存电路，每个数据锁存电路被分配给数据处理器。 以行地址RA和列地址CA的复用方式给出地址。 当选择数据锁存电路时给定行地址RA时，更新每个数据锁存电路中的数据。

公开(公告)号：US5388229A

公开(公告)日：1995-02-07

申请号：US136095

申请日：1993-10-14

申请人： Yukio Hyouga ,  Katsuyuki Kaneko

发明人： Yukio Hyouga ,  Katsuyuki Kaneko

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： In a data transmission device, before the starting of data transmission, a data conduct device detects an external bus, and an address comparator section compares the value of the address signal line with the output values of the parameter memory section. As the result of the comparison, when it is judged that the data to be transmitted is present on the external bus, the address comparator section transmits a write-execution signal to a bus control unit so that the bus control unit writes the data present on the external bus together with the validity bit thereof into the data memory device. In the period of data transmission, when the data assigned to the address produced by an address generator is present in the data memory device, the data is transmitted to the external destination, and on the other hand, when the data assigned to the address is absent in the data memory device, the bus control unit gains access to the external memory for obtaining the data corresponding to the address, so that the data obtained from the external memory is transmitted to the external destination.

摘要翻译： 在数据传输装置中，在数据传输开始之前，数据传导装置检测外部总线，地址比较部分将地址信号线的值与参数存储部分的输出值进行比较。 作为比较的结果，当判断要发送的数据存在于外部总线上时，地址比较器部分向总线控制单元发送写入执行信号，使得总线控制单元将存在的数据写入 外部总线及其有效位连接到数据存储器件中。 在数据传输期间，当分配给由地址生成器产生的地址的数据存在于数据存储装置中时，数据被发送到外部目的地，另一方面，当分配给地址的数据是 在数据存储装置中不存在，总线控制单元获得对外部存储器的访问以获得对应于该地址的数据，使得从外部存储器获得的数据被发送到外部目的地。