发明授权
US4719600A Sense circuit for multilevel storage system 失效
多电平存储系统感应电路

Sense circuit for multilevel storage system
摘要:
An improved sense circuit for determining the data state of a memory cell in a multilevel storage system is disclosed. The sense circuit includes at least two differential voltage level sensing circuits. A first differential voltage level sensing circuit compares the relative magnitudes of a data input signal voltage level corresponding to a particular memory cell charge level and a first reference voltage level, thereby providing at least one first binary data output signal. The first binary data output signal is then used to generate a second reference voltage level having a magnitude different from that of the first reference voltage level. A second differential voltage sensing level circuit compares the relative magnitudes of an adjusted data input signal voltage level and a second reference voltage level, thereby providing at least one second binary data output signal. The adjusted data input signal corresponds to a function of the first data input signal. Hence, the binary data output signals provided correspond to the charge level stored in the memory cell.
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