An error correcting logic circuit for masking faults on dual redundant interconnections. Both interconnections are inmput to a NAND or AND circuit which includes pull-up resistors to a high potential. The outputs of all the NAND circuits are connected to dual redundant logic circuits, each of which has an emitter-follower output with a load resistor to ground. The outputs of the redundant logic circuits provide the redundant interconnections to other similar error correcting logic circuits.