公开(公告)号：US20160134287A1

公开(公告)日：2016-05-12

申请号：US14997887

申请日：2016-01-18

申请人： Northwestern University

发明人： Joseph S. Friedman ,  Gokhan Memik ,  Bruce W. Wessels

IPC分类号： H03K19/094 ,  H03K19/086 ,  H01L29/82 ,  H01L29/78 ,  H01L29/66 ,  H01L29/73

CPC分类号： H03K19/094 ,  H01L29/66984 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/82 ,  H03K19/082 ,  H03K19/086

摘要： A switch comprising a spin-transistor and a first control wire. The spin-transistor is configured so that when a magnetic field applied to the spin-transistor is less than a threshold value, the transistor is in a conductive state in which electric current flows through the spin-transistor. When the magnetic field applied to the spin-transistor is greater than the threshold value, the spin-transistor is in a resistive state in which the electric current flowing through the spin-transistor is substantially reduced. The first control wire is for receiving a current to affect the magnetic field applied to the spin-transistor.

摘要翻译： 一种包括自旋晶体管和第一控制线的开关。 自旋晶体管被配置为使得当施加到自旋晶体管的磁场小于阈值时，晶体管处于电流流过自旋晶体管的导通状态。 当施加到自旋晶体管的磁场大于阈值时，自旋晶体管处于电阻状态，其中流过自旋晶体管的电流显着减小。 第一控制线用于接收电流以影响施加到自旋晶体管的磁场。

公开(公告)号：US08937495B1

公开(公告)日：2015-01-20

申请号：US13852775

申请日：2013-03-28

申请人： Russell D. Wyse ,  Mark A. Willi ,  Michael L. Hageman

发明人： Russell D. Wyse ,  Mark A. Willi ,  Michael L. Hageman

IPC分类号： H03K19/086 ,  H03K19/00

CPC分类号： H03K19/0013

摘要： Emitter-coupled logic circuits and systems that include such circuits are provided. Some emitter-coupled logic circuits include a plurality of fT-doubler circuits. Each fT-doubler circuit includes a plurality of transistors coupled to one another in an arrangement such that the plurality of transistors are configured to behave as a single enhanced transistor that has an effective unity current gain frequency that is higher than if a single transistor were used in its place. The fT-doubler circuits are configured to increase an operating frequency capability of the emitter-coupled logic circuit. Some emitter-coupled logic circuits include a plurality of cascode amplifier circuits. Each cascode amplifier circuit includes multiple transistors. An emitter of at least one first transistor of the plurality of transistors is coupled to a collector of at least one second transistor of the plurality of transistors Some emitter-coupled logic circuits may include both fT-doubler circuits and cascode amplifier circuits.

摘要翻译： 提供了包括这种电路的发射极耦合逻辑电路和系统。 一些发射极耦合逻辑电路包括多个fT倍增电路。 每个fT倍增电路包括多个晶体管，这些晶体管以这样的结构彼此耦合，使得多个晶体管被配置为表现为具有比单个晶体管被使用的有效单位电流增益频率高的单个增强型晶体管 在它的位置。 fT倍增电路被配置为增加发射极耦合逻辑电路的工作频率能力。 一些发射极耦合逻辑电路包括多个共源共栅放大器电路。 每个共源共栅放大器电路包括多个晶体管。 多个晶体管中的至少一个第一晶体管的发射极耦合到多个晶体管的至少一个第二晶体管的集电极。一些发射极耦合逻辑电路可以包括fT倍增电路和共源共栅放大器电路。

公开(公告)号：US07821300B2

公开(公告)日：2010-10-26

申请号：US12327786

申请日：2008-12-03

申请人： Dan P. Bernard ,  John C. Schiff ,  Glen A. Wiedemeier

发明人： Dan P. Bernard ,  John C. Schiff ,  Glen A. Wiedemeier

IPC分类号： H03K19/086 ,  H03B1/00

CPC分类号： H03K19/018528 ,  H03K19/09436

摘要： A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.

摘要翻译： 系统包括被配置为接收第一CML逻辑系列的第一偏置信号和第一CML信号的第一CML缓冲器。 第一CML缓冲器基于第一CML信号和第一偏置信号产生第一CML逻辑系列的第二CML信号。 第一耦合电容器模块耦合到第一CML缓冲器。 第一耦合电容器模块接收第二CML信号并且基于第二CML信号产生第三CML信号。 第二CML缓冲器耦合到耦合电容器模块并且接收第二偏置信号和第三CML信号，产生第二CML逻辑系列的第四CML信号。 反馈模块耦合到第二CML缓冲器并且接收产生第五CML信号的第四CML信号。 第二CML缓冲器基于第二偏置信号，第三CML信号和第五CML信号产生第四CML信号。

公开(公告)号：US07576567B2

公开(公告)日：2009-08-18

申请号：US11421239

申请日：2006-05-31

申请人： Jian Hong Jiang

发明人： Jian Hong Jiang

IPC分类号： H03K19/094 ,  H03K19/20 ,  H03K19/086

CPC分类号： H03K19/094 ,  H03K19/018528

摘要： A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

摘要翻译： 用于高速数字传输的低电压差分信号驱动器包括可操作以接收第一类型的信号并将信号转换为第二类型的第一转换器，以及耦合到第一转换器的共源共栅电流镜。 共源共栅电流镜提供了增加差分输出电压的阻抗电平。

公开(公告)号：US07564270B1

公开(公告)日：2009-07-21

申请号：US11769088

申请日：2007-06-27

申请人： Xiaohu Zhang ,  George Ansel

发明人： Xiaohu Zhang ,  George Ansel

IPC分类号： H03K19/086

CPC分类号： H03K19/00315 ,  H03K19/00384

摘要： A driver circuit is provided herein. In general, the driver circuit includes a driver portion, a common mode feedback portion and a current replication portion. The feedback portion receives a common mode voltage (vcm) from the driver portion and an alternative common mode voltage (vcm_alt) from the current replication portion. The feedback portion selects one of the common mode voltages for comparison with a reference voltage and generates a feedback bias signal (vcmfb) based on a voltage difference there between. When the driver circuit is enabled, the actual common mode voltage (vcm) is used to maintain the output common mode voltage around the reference voltage. When the driver circuit is disabled, the alternative common mode voltage (vcm_alt) is used to keep the bias signal (vcmfb) from drifting away.

摘要翻译： 本文提供了驱动电路。 通常，驱动器电路包括驱动器部分，共模反馈部分和当前复制部分。 反馈部分接收来自驱动器部分的共模电压（vcm）和来自当前复制部分的替代共模电压（vcm_alt）。 反馈部分选择用于与参考电压进行比较的共模电压之一，并基于它们之间的电压差产生反馈偏置信号（vcmfb）。 当驱动器电路使能时，实际的共模电压（vcm）用于维持参考电压周围的输出共模电压。 当驱动器电路被禁用时，替代共模电压（vcm_alt）用于保持偏置信号（vcmfb）不被漂移。

公开(公告)号：US20060279337A1

公开(公告)日：2006-12-14

申请号：US10572612

申请日：2004-09-10

申请人： Lionel Guiraud

发明人： Lionel Guiraud

IPC分类号： H03K19/086

CPC分类号： H03K19/212 ,  H03K19/086

摘要： The invention relates to an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means. The discriminating stage comprises four transistors (Q8, Q9, Q10, Q11) each having first electrodes (83, 93, 103, 113) and second electrodes (81, 91, 101, 111) and a respective gate electrode (82, 92, 102, 112). The first electrodes of said four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of said four transistors respectively.

摘要翻译： 本发明涉及一种包括差分信号输入装置，组合级，识别级和差分信号输出装置的电子电路。 鉴别级包括四个晶体管（Q 8，Q 9，Q 10，Q 11），每个具有第一电极（83,93,103,113）和第二电极（81,91,101,111）和相应的栅电极 82，92，102，112）。 所述四个晶体管的第一电极被连接到公共节点。 组合级被布置成将差分输入信号转换成分别施加到所述四个晶体管中的一些的栅电极的栅极信号。

公开(公告)号：US07145366B2

公开(公告)日：2006-12-05

申请号：US10954619

申请日：2004-09-30

申请人： Sébastien Rieubon ,  Serge Ramet ,  Philippe Level

发明人： Sébastien Rieubon ,  Serge Ramet ,  Philippe Level

IPC分类号： H03K19/086 ,  H03K19/20

CPC分类号： H03K17/04166 ,  H03K17/04113 ,  H03K19/0136 ,  H03K19/086

摘要： An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.

摘要翻译： 电子电路包括至少一个差分对晶体管，控制晶体管开关，第一电流源和第二电流源。 第二电流源连接到一对晶体管的公共发射极节点，以便在开关操作期间加速寄生电容的放电。

公开(公告)号：US07132857B2

公开(公告)日：2006-11-07

申请号：US10436737

申请日：2003-05-14

申请人： Kevin Joseph Jurek

发明人： Kevin Joseph Jurek

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/20 ,  H03K19/086

CPC分类号： H04L25/45 ,  H04L25/028

摘要： A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is coupled for shifting the common mode potential of the input signal to produce a shifted signal (VSH0, VSH1). A second gate (22) has an input (27, 28) that receives the shifted signal and an output coupled to the output of the first gate.

摘要翻译： 接收器电路（12）包括接收输入信号（V IN1，V IN1）的第一门（24），并具有用于提供（32,34）的输出 一个输出信号（V ，V> G1）。 移位电路（20）被耦合以移位输入信号的共模电位以产生移位信号（V SH1，V SUB1）。 第二栅极（22）具有接收移位信号的输入端（27,28）和耦合到第一栅极输出端的输出端。

公开(公告)号：US07098697B2

公开(公告)日：2006-08-29

申请号：US10857238

申请日：2004-05-28

申请人： Daniel Kucharski ,  Kevin Kornegay

发明人： Daniel Kucharski ,  Kevin Kornegay

IPC分类号： H03K19/086

CPC分类号： H03K3/2885 ,  H03K17/6264 ,  H03K19/001 ,  H03K19/086 ,  H03K19/212

摘要： A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%–50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.

摘要翻译： 公开了一种用于高速低电压逻辑电路的电路拓扑，其将堆叠的有源电路元件的电平数量从3减少到2.提供了各种逻辑功能的电路，包括锁存器，异或门，组合XOR 并锁存，复用器和解复用器。 根据本发明的原理构建的电路已经以40GHz的速度运行。 电路拓扑可以在低至2V的电源电压（基于硅或硅锗器件）下工作，并且可根据逻辑功能提供25％-50％以上的功率节省。 在一些实施例中，可以提供包括单端或差分输入的电路。

公开(公告)号：US20050162202A1

公开(公告)日：2005-07-28

申请号：US11085559

申请日：2005-03-22

申请人： Norihito Suzuki

发明人： Norihito Suzuki

IPC分类号： H03L7/093 ,  H03L7/089 ,  H03L7/095 ,  H03K19/086

CPC分类号： H03L7/0891 ,  H03L7/095

摘要： A charge pump circuit able to enhance the rising and falling characteristics of a current output, drive the current output with a short pulse, reduce leakage current at the OFF time when a current is not output, and realize a reduction of a power consumption and a PLL circuit using same. By outputting a charge current or a discharge current in accordance with an up signal or a down signal and turning on a third transistor (PC, NC) at the OFF time when the current is not output, an inverse bias voltage is supplied between a gate and a source of the second transistor (PA, NA), whereby a reduction of the leakage current can be realized. When the second or third transistor is switched in accordance with the up signal or the down signal, the timing of the control signal is appropriately controlled, simultaneous turning on of the second and third transistors can be avoided, release or injection of charges from and to the output terminal of the charge pump circuit can be prevented, and the stability of an oscillation frequency of a VCO can be improved.