发明授权
US4729966A Process for manufacturing a Schottky FET device using metal sidewalls as
gates
失效
使用金属侧壁作为栅极制造肖特基FET器件的工艺
- 专利标题： Process for manufacturing a Schottky FET device using metal sidewalls as gates
- 专利标题（中）： 使用金属侧壁作为栅极制造肖特基FET器件的工艺
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申请号： US843833申请日： 1986-03-26
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公开(公告)号： US4729966A公开(公告)日： 1988-03-08
- 发明人: Yutaka Koshino , Tatsuo Akiyama , Shunichi Hiraki
- 申请人： Yutaka Koshino , Tatsuo Akiyama , Shunichi Hiraki
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX58-153166 19830824
- 主分类号： H01L29/812
- IPC分类号： H01L29/812 ; H01L21/28 ; H01L21/285 ; H01L21/338 ; H01L29/417 ; H01L21/225 ; H01L29/72 ; H01L29/80
摘要：
A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film. The drain region consists of a high-concentration impurity layer, which is formed such that it is surrounded by the channel positioned inside the substrate on the inside of the second insulative film.
公开/授权文献
- US4134539A Code identification apparatus 公开/授权日：1979-01-16
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