A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) either color codes each representative of a color of each display element, or amplitude data representative of amplitudes of a video signal to be reproduced. When displaying an image based on the color codes, the color codes are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. This output data is summed by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. When displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data. The digital color encoder multiplies the gradation data by other proper coefficients so that data proportional in value to the gradation data are obtained at the output of the adder circuit. This data is converted into an analog signal to thereby reproduce the video signal.