发明授权
- 专利标题： Lead arrangement for reducing voltage variation
- 专利标题（中）： 用于降低电压变化的引线排列
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申请号： US853929申请日： 1986-04-21
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公开(公告)号： US4748494A公开(公告)日： 1988-05-31
- 发明人: Toshio Yamada , Hiroyuki Itho , Masayoshi Yagyu , Akira Masaki
- 申请人： Toshio Yamada , Hiroyuki Itho , Masayoshi Yagyu , Akira Masaki
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX60-82357 19850419
- 主分类号： H01L21/822
- IPC分类号： H01L21/822 ; G11C11/401 ; G11C11/407 ; H01L21/8222 ; H01L23/528 ; H01L27/04 ; H01L27/082 ; H01L29/52 ; H01L27/10
摘要：
A semiconductor device includes a plurality of circuit groups constituting an integrated circuit and each constituted by a plurality of circuit blocks and a bias circuit which applies a bias potential to said circuit blocks. The device further includes a plurality of power buses provided above the circuit groups through an insulating layer so as to feed power to circuit elements in the circuit groups. At least one of the power buses is constituted by a first bus for feeding power to the circuit groups and a plurality of second buses respectively provided for the circuit groups so that each second bus receives power from the first bus and feeds power to circuit elements in the corresponding circuit group. Each of the second buses is connected to the first bus at a predetermined position on the corresponding circuit group.
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