Lead arrangement for reducing voltage variation
    1.
    发明授权
    Lead arrangement for reducing voltage variation 失效
    用于降低电压变化的引线排列

    公开(公告)号:US4748494A

    公开(公告)日:1988-05-31

    申请号:US853929

    申请日:1986-04-21

    CPC分类号: H01L23/5286 H01L2924/0002

    摘要: A semiconductor device includes a plurality of circuit groups constituting an integrated circuit and each constituted by a plurality of circuit blocks and a bias circuit which applies a bias potential to said circuit blocks. The device further includes a plurality of power buses provided above the circuit groups through an insulating layer so as to feed power to circuit elements in the circuit groups. At least one of the power buses is constituted by a first bus for feeding power to the circuit groups and a plurality of second buses respectively provided for the circuit groups so that each second bus receives power from the first bus and feeds power to circuit elements in the corresponding circuit group. Each of the second buses is connected to the first bus at a predetermined position on the corresponding circuit group.

    摘要翻译: 半导体器件包括构成集成电路的多个电路组,并且各个电路组由多个电路块和向所述电路块施加偏置电位的偏置电路构成。 该装置还包括多个电源总线,其通过绝缘层设置在电路组之上,以便向电路组中的电路元件供电。 电力总线中的至少一个由用于向电路组供电的第一总线和分别为电路组提供的多个第二总线构成,使得每个第二总线从第一总线接收电力并将电力馈送到电路元件 相应的电路组。 每个第二总线在相应电路组上的预定位置连接到第一总线。

    Flip-flop circuit
    2.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号:US4868420A

    公开(公告)日:1989-09-19

    申请号:US273729

    申请日:1988-11-18

    IPC分类号: H03K3/037 H03K3/2885

    CPC分类号: H03K3/2885 H03K3/0375

    摘要: An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.

    摘要翻译: 提供一种改进的触发器电路,其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。 触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。 逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。 逻辑门的输出通过反馈回路输入到第一逻辑电路,反馈回路设置在第一逻辑电路的输出端和输入端之间,并包括逻辑门。 根据本发明的电路结构,可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。

    Transistor circuit with improved .alpha. ray resistant properties
    4.
    发明授权
    Transistor circuit with improved .alpha. ray resistant properties 失效
    具有改进的抗α射线特性的晶体管电路

    公开(公告)号:US4942320A

    公开(公告)日:1990-07-17

    申请号:US208118

    申请日:1988-06-17

    摘要: A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit. It is disposed in a feedback part and used as a constant current source in a logic circuit comprising a logic part consisting of a differential transistor circuit and the feedback part for negatively feeding back the in-phase output of the differential transistor circuit.

    摘要翻译: 本发明的晶体管电路包括用于在其基极处接收第一偏压的第一晶体管,连接到第一晶体管的集电极的电阻器件和连接到第一晶体管和电阻器装置之间的结的钳位装置, 电阻器的端子与其与第一晶体管的连接相对。 当在第一晶体管中产生由于α射线引起的噪声电流并且输出降低时,钳位装置以使得电流流过钳位装置并防止输出变化的方式工作。 本发明的晶体管电路连接到电阻器或晶体管,并作为恒流电路用于向电阻器或晶体管提供电流,使得流过其中的电流恒定。 例如,它被用作射极跟随器的恒流源来构成电平移位电路。 它被布置在反馈部分中,并在逻辑电路中用作恒流源,该逻辑电路包括由差分晶体管电路和反馈部分组成的逻辑部分,用于对差分晶体管电路的同相输出进行负反馈。

    Integrated Circuit with Multidimensional Switch Topology
    5.
    发明申请
    Integrated Circuit with Multidimensional Switch Topology 失效
    多维开关拓扑集成电路

    公开(公告)号:US20090009215A1

    公开(公告)日:2009-01-08

    申请号:US11596011

    申请日:2005-03-28

    IPC分类号: H03K19/177 G06F17/50

    摘要: An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.

    摘要翻译: FPGA在其布线架构中需要极大数量的开关,因此显示出低的逻辑密度和低的运行速度。 高集成度FPGA的趋势越来越明显。 3维FPGA正在注意其运行速度和逻辑密度的潜在改进。 然而,三维一体化处理成品率低,难以适应具有精细特征的装置的生产。 此外,热辐射的困难对堆叠数量施加了限制。 本发明利用3维FPGA的优点来提供高速/高集成度的FPGA,并且解决了制造过程中的难度。 本发明通过提出一种用于FPGA的设计方法来解决问题,其中高维FPGA开关拓扑嵌入在低维集成电路中,以及包括FPGA的半导体集成电路,其中高维FPGA开关拓扑嵌入在较低维数 三维集成电路。

    Parallel folding apparatus of folding machine
    6.
    发明授权
    Parallel folding apparatus of folding machine 有权
    平折机折叠机

    公开(公告)号:US07217233B2

    公开(公告)日:2007-05-15

    申请号:US11116368

    申请日:2005-04-28

    IPC分类号: B31F1/08

    摘要: A parallel folding apparatus of a folding machine comprises a first cylinder in contact with a second cylinder. A guide plate guides a signature transported on the lower circumferential surface of the second cylinder after being double-folded by grippers of the second cylinder in cooperation with knives of the first cylinder. The guide plate comprises a stationary guide located downstream, in the rotating direction, of the point of contact between the first cylinder and the second cylinder and disposed continuously along the circumferential surfaces of the first cylinder and the second cylinder, and a moving guide movable in accordance with the operating speed of the folding machine between a position, closer to the circumferential surface of the first cylinder than the stationary guide, and a position, more remote from the circumferential surface of the first cylinder than the stationary guide.

    摘要翻译: 折叠机的平行折叠装置包括与第二气缸接触的第一气缸。 与第一气缸的刀片协作,引导板引导在第二气缸的夹持器双重折叠之后在第二气缸的下圆周表面上传送的标记。 引导板包括位于第一气缸和第二气缸之间的接触点的沿旋转方向的下游并沿着第一气缸和第二气缸的周向表面连续设置的静止引导件,以及可移动的移动引导件 根据折叠机在比第一圆柱体的圆周表面更靠近固定导轨的位置之间的操作速度以及比第一圆柱体的圆周表面更远离静止导轨的位置。

    Cooling module for integrated circuit chips
    7.
    发明授权
    Cooling module for integrated circuit chips 失效
    集成电路芯片的冷却模块

    公开(公告)号:US4644385A

    公开(公告)日:1987-02-17

    申请号:US665548

    申请日:1984-10-26

    摘要: This invention concerns a cooling module for integrated circuit chips, characterized in that it is provided with cooling members through which a coolant circulates, and which are connected directly, or via insulating plates, to a plurality of integrated circuit chips mounted on a wiring substrate, and pipes which introduce the coolant into the cooling members and which have a resiliency which is high enough to enable the pipes to expand and contract in the direction perpendicular to the wiring substrate.

    摘要翻译: 本发明涉及一种用于集成电路芯片的冷却模块,其特征在于,其具有冷却元件,冷却器通过该冷却元件循环并直接连接或经由绝缘板连接到安装在布线基板上的多个集成电路芯片, 以及将冷却剂引入冷却部件中并且具有足够高的弹性以使管能够在垂直于布线基板的方向膨胀和收缩的管道。

    Liquid crystal cell with twist angle from 180 to 270 degrees and twisted optical compensating element
    8.
    发明授权
    Liquid crystal cell with twist angle from 180 to 270 degrees and twisted optical compensating element 失效
    扭转角为180〜270度的液晶单元和扭曲光学补偿元件

    公开(公告)号:US07019804B2

    公开(公告)日:2006-03-28

    申请号:US10490709

    申请日:2002-09-06

    IPC分类号: G02F1/1335

    摘要: A liquid crystal display device has a liquid crystal cell, a liquid crystalline substance layer, a pair of polarizers, and an optical compensation element. The twist angle of the liquid crystal cell is set to 180 to 270 degrees. The optical compensation element has a twisted structure twisted in the opposite direction to that of the liquid crystal cell. The difference in the absolute values of the twist angles between the liquid crystal cell and the optical compensation element is from 40 to 100 degrees. The difference in retardation at a wavelength λ=550 nm between the liquid crystal cell and the optical compensation element is from 100 to 250 nm. When the absolute values of the differences in retardation at wavelengths λ of 400 nm and 550 nm between the liquid crystal cell and the optical compensation element are represented by ΔR(400) and ΔR(550), respectively, and the ratio D therebetween is represented by D=ΔR(400)/ΔR(550), D is within the range of 0.5 to 1.0.

    摘要翻译: 液晶显示装置具有液晶单元,液晶物质层,一对偏振器和光学补偿元件。 液晶单元的扭转角度设定为180〜270度。 光学补偿元件具有与液晶单元相反方向扭转的扭曲结构。 液晶单元和光学补偿元件之间的扭转角的绝对值的差为40〜100度。 在液晶单元和光学补偿元件之间的波长λ= 550nm处的延迟差为100〜250nm。 当分别用DeltaR(400)和DeltaR(550)表示液晶单元和光学补偿元件之间在400nm和550nm波长λ处的延迟差的绝对值,并且其间的比率D被表示 通过D = DeltaR(400)/ DeltaR(550),D在0.5至1.0的范围内。