A master slice type semiconductor circuit device including a memory block having at least one memory circuit; one conductive layer provided to peripheral portions of the memory circuit and used as an input portion thereto; power source lines provided to the peripheral portion of the memory circuit and formed by a conductive layer different from the conductive layer of the input portion; and a contact hole for connecting between the two conductive layers at a selected input portion. The selected input portion connected by the contact hole is set or clamped to a predetermined logic level by the power source line. This enables a change of the memory capacity or the function of the memory block to satisfy customer requirements.