发明授权
US4789951A Programmable array logic cell 失效
可编程阵列逻辑单元

Programmable array logic cell
摘要:
A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.
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