发明授权
US4813022A Static memory with pull-up circuit for pulling-up a potential on a bit
line
失效
具有上拉电路的静态存储器，用于提升位线上的电位
- 专利标题： Static memory with pull-up circuit for pulling-up a potential on a bit line
- 专利标题（中）： 具有上拉电路的静态存储器，用于提升位线上的电位
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申请号： US136769申请日： 1987-12-22
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公开(公告)号： US4813022A公开(公告)日： 1989-03-14
- 发明人: Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
- 申请人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX61-315317 19861226
- 主分类号： G11C11/417
- IPC分类号： G11C11/417 ; G11C7/12 ; G11C11/41 ; G11C11/413 ; G11C11/419 ; G11C7/00 ; G11C11/34
摘要：
The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.
公开/授权文献
- US4306728A Sliding surface packing 公开/授权日：1981-12-22
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