公开(公告)号：US5808699A

公开(公告)日：1998-09-15

申请号：US688305

申请日：1996-07-20

申请人： Susumu Tsujihara ,  Ikunori Inoue ,  Yoshio Seki ,  Mitsuo Isobe

发明人： Susumu Tsujihara ,  Ikunori Inoue ,  Yoshio Seki ,  Mitsuo Isobe

IPC分类号： H04N5/18 ,  H04N5/202 ,  H04N5/57

CPC分类号： H04N5/18 ,  H04N5/202 ,  H04N5/57

摘要： A visual image signal processing apparatus includes: an overlaying unit for overlaying a brightness reference signal at a predetermined position in a fly-back period of an input visual image signal; a first clamping unit for clamping an output from the overlaying unit at a predetermined clamping voltage; a detecting unit for applying an output from the first clamping unit to a driving electrode of a cathode ray tube and for detecting a beam current flowing based on the brightness reference signal overlaid in the input visual image signal; and a second clamping unit for controlling the predetermined clamp voltage based on the beam current detected by the detecting unit.

摘要翻译： 视觉图像信号处理装置包括：重叠单元，用于在输入视觉信号的回扫周期中将亮度参考信号叠加在预定位置; 第一夹紧单元，用于以预定的钳位电压钳位来自覆盖单元的输出; 检测单元，用于将来自第一夹持单元的输出施加到阴极射线管的驱动电极，并用于基于重叠在输入视觉信号中的亮度参考信号来检测流过的束流; 以及第二夹持单元，用于基于由检测单元检测到的束电流来控制预定的钳位电压。

公开(公告)号：US4879686A

公开(公告)日：1989-11-07

申请号：US163750

申请日：1988-03-03

申请人： Azuma Suzuki ,  Takayuki Ootani ,  Mitsuo Isobe

发明人： Azuma Suzuki ,  Takayuki Ootani ,  Mitsuo Isobe

IPC分类号： G11C11/401 ,  G11C7/20 ,  G11C11/419

CPC分类号： G11C7/20 ,  G11C11/419

摘要： A semiconductor memory device comprising a memory cell-selecting section, an input supply control section, and a bit-line potential control section. The memory cell-selecting section includes a row decoder and a first gate circuit coupled to the output thereof. The memory cell-selecting section drives all the memory cells making up the memory device, when it is set in the mode for clearing the memory device, and the input data supply control section disconnects a pair of bit lines from a write circuit when the control section is set in this same mode. When the bit-line potential control section is set in the memory-clearing mode, it sets the potential of one of the bit lines at a high level, and the potential of the other bit line at a low potential.

摘要翻译： 一种半导体存储器件，包括存储单元选择部分，输入电源控制部分和位线电位控制部分。 存储单元选择部分包括与其输出耦合的行解码器和第一门电路。 当存储单元选择部分被设置为用于清除存储器件的模式时，驱动构成存储器件的所有存储器单元，并且当控制器的控制被切换时，输入数据提供控制部件从写入电路断开一对位线 部分设置在同一模式。 当位线电位控制部分设定在存储器清零模式时，它将位线之一的电位设置在高电平，另一位线的电位设置在低电位。

公开(公告)号：US4858197A

公开(公告)日：1989-08-15

申请号：US198052

申请日：1988-05-24

申请人： Akira Aono ,  Mitsuo Isobe

发明人： Akira Aono ,  Mitsuo Isobe

IPC分类号： G11C7/10 ,  G11C8/18

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/18

摘要： In an output buffer control circuit of a memory, the set/reset state of a flip-flop is controlled by an address transition detection output and a read detection output supplied when completion of data read from a memory cell is detected, and the active/inactive state of an output buffer for outputting the readout data from the memory cell is controlled by an output from the flip-flop. According to this arrangement, when an address input transits and the address transition detection output is enabled, the output buffer is inactivated. When data is read out from the memory cell and the read detection output is enabled after the address input transits, the output buffer can be activated.

摘要翻译： 在存储器的输出缓冲器控制电路中，触发器的置位/复位状态由地址转变检测输出和当检测到从存储器单元读取的数据完成时提供的读取检测输出来控制， 用于从存储单元输出读出数据的输出缓冲器的非活动状态由触发器的输出控制。 根据该结构，当地址输入转换并且地址转换检测输出被使能时，输出缓冲器被禁止。 当从存储单元中读出数据并且在地址输入转换后读取检测输出被使能时，可以激活输出缓冲器。

公开(公告)号：US4813022A

公开(公告)日：1989-03-14

申请号：US136769

申请日：1987-12-22

申请人： Masataka Matsui ,  Tetsuya Iizuka ,  Jun-ichi Tsujimoto ,  Takayuki Ohtani ,  Mitsuo Isobe

发明人： Masataka Matsui ,  Tetsuya Iizuka ,  Jun-ichi Tsujimoto ,  Takayuki Ohtani ,  Mitsuo Isobe

IPC分类号： G11C11/417 ,  G11C7/12 ,  G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C7/12 ,  G11C11/419

摘要： The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.

摘要翻译： 位线的每个充电/均衡MOS晶体管的阈值电压小于通常的ON型位线上拉晶体管的阈值电压。 通过这一功能，在读出操作期间，没有电流从电源VDD流过位线。 可以高速地增加一对位线之间的电压差，从而增加读出速度。

公开(公告)号：US4697112A

公开(公告)日：1987-09-29

申请号：US878372

申请日：1986-06-25

申请人： Takayuki Ohtani ,  Mitsuo Isobe ,  Akira Aono ,  Nobuaki Urakawa

发明人： Takayuki Ohtani ,  Mitsuo Isobe ,  Akira Aono ,  Nobuaki Urakawa

IPC分类号： H03K5/02 ,  G11C11/409 ,  G11C11/419 ,  H03F3/45 ,  H03K3/356

CPC分类号： H03F3/45183 ,  H03K3/356104 ,  H03F2203/45394 ,  H03F2203/45466 ,  H03F2203/45644 ,  H03F2203/45674 ,  H03F2203/45726

摘要： There is disclosed a sense amplifier characterized by comprising a pull-up circuit. The pull-up circuit comprises a first transistor arranged between the first of a pair of output nodes and a pull-up power source potential node, and a second transistor arranged between the second of the pair of output nodes and the pull-up power source potential node. The gate of the first transistor is connected to the second output node and the gate of the second transistor is connected to the first output node.

摘要翻译： 公开了一种感测放大器，其特征在于包括一个上拉电路。 上拉电路包括布置在一对输出节点之间的第一个和上拉电源电势节点之间的第一晶体管，以及布置在该对输出节点中的第二个和上拉电源之间的第二晶体管 潜在节点。 第一晶体管的栅极连接到第二输出节点，第二晶体管的栅极连接到第一输出节点。

公开(公告)号：US3953884A

公开(公告)日：1976-04-27

申请号：US514371

申请日：1974-10-15

申请人： Mitsuo Isobe ,  Toshihiko Yoshino

发明人： Mitsuo Isobe ,  Toshihiko Yoshino

IPC分类号： H04N9/67 ,  H04N9/52

CPC分类号： H04N9/67

摘要： A video amplifier is disclosed wherein the luminance signal is applied to the collector circuit of a differential amplifier comprising two transistors, the color difference signal is applied to the base of one of the two transistors, and the primary color signal is derived across a load resistor coupled to the collector circuit.

摘要翻译： 公开了一种视频放大器，其中将亮度信号施加到包括两个晶体管的差分放大器的集电极电路，色差信号被施加到两个晶体管之一的基极，并且原色信号通过负载电阻 耦合到集电极电路。

公开(公告)号：US5414330A

公开(公告)日：1995-05-09

申请号：US20567

申请日：1993-02-22

申请人： Susumu Tsujihara ,  Mitsuo Isobe ,  Hiroyosi Shimosaka ,  Hiroshi Taniguchi

发明人： Susumu Tsujihara ,  Mitsuo Isobe ,  Hiroyosi Shimosaka ,  Hiroshi Taniguchi

IPC分类号： H04N3/22 ,  H04N3/233 ,  H04N9/24 ,  H04N9/28 ,  G09G1/04 ,  H01J29/10 ,  H01J31/26

CPC分类号： H04N9/24 ,  H04N3/22 ,  H04N3/2335 ,  H04N9/28

摘要： A cathode ray tube control apparatus includes phosphor display screen, three electron guns for emitting R, G, B electron beams to the display screen, a shadow mask placed between the electron guns and the display screen, and index phosphors deposited on the shadow mask and having at least two line elements diagonal to a horizontal scanning direction of the electron beam for generating a signal according to the electron beam scan. Further provided are detector for detecting beam crossing points over the index phosphor, and correction circuit for correcting the deflection of the electron beam based on the detected beam crossing points.

摘要翻译： 阴极射线管控制装置包括荧光显示屏，用于向显示屏发射R，G，B电子束的三个电子枪，放置在电子枪和显示屏之间的荫罩，以及沉积在荫罩上的折射荧光体， 具有与电子束的水平扫描方向对角的至少两个线元件，用于根据电子束扫描产生信号。 还提供了用于检测指示荧光体上的光束交叉点的检测器，以及用于基于检测到的光束交叉点校正电子束的偏转的校正电路。

公开(公告)号：US5003389A

公开(公告)日：1991-03-26

申请号：US437688

申请日：1989-11-17

申请人： Mitsuo Isobe ,  Masanori Hamada ,  Katsumi Morita ,  Yuichi Ninomiya

发明人： Mitsuo Isobe ,  Masanori Hamada ,  Katsumi Morita ,  Yuichi Ninomiya

IPC分类号： H04N19/102 ,  H04N5/14 ,  H04N5/46 ,  H04N7/015 ,  H04N7/24 ,  H04N11/00 ,  H04N11/24 ,  H04N19/00 ,  H04N19/132 ,  H04N19/137 ,  H04N19/196 ,  H04N19/42 ,  H04N19/423 ,  H04N19/59 ,  H04N19/80

CPC分类号： H04N5/144 ,  H04N5/46 ,  H04N7/0152 ,  H04N7/24

摘要： An image signal processing apparatus is provided which is applicable to a motion adaptive Y/C separation of an NTSC signal and a time-domain/spatial interpolation of a high definition television signal band-compressed by sub-Nyquist sub-sampling. The apparatus includes a still image processing circuit having frame memories, a motion image processing circuit having a line memory, a mixing circuit for mixing outputs of these processing circuits, a circuit for detecting image motion of an input image signal and applying a resultant control signal to the mixing circuit, and a signal mode control circuit for selectively adapting the image processing circuits for the processing of the NTSC signal or the high definition television signal. The motion detecting circuit includes a narrow band detecting circuit for producing a one-frame interval difference signal of a signal spectrum of a pure low frequency component from the NTSC signal or the high definition television signal respectively, a wide band detecting circuit for a two-frame interval difference signal and a composition circuit for composing outputs of these detecting circuits. The still image processing circuit, motion image processing circuit and mixing circuit are adapted to operate for the Y/C separation with the NTSC signal and for the interpolation of the high definition television signal, respectively.

公开(公告)号：US4963969A

公开(公告)日：1990-10-16

申请号：US314087

申请日：1989-02-23

申请人： Hiromu Kitaura ,  Mitsuo Isobe ,  Yuichi Ninomiya ,  Yoshimichi Ohtsuka ,  Yoshinori Izumi

发明人： Hiromu Kitaura ,  Mitsuo Isobe ,  Yuichi Ninomiya ,  Yoshimichi Ohtsuka ,  Yoshinori Izumi

IPC分类号： H04N5/04 ,  H04N5/52 ,  H04N7/015

CPC分类号： H04N5/52

摘要： Disclosed is an automatic gain control device which comprises: a first amplitude detection circuit for detecting an average amplitude value of a television video signal, a peak amplitude value of the same television video signal, or a value obtained by mixing the average amplitude value and the peak amplitude value with a predetermined mixing ratio; a second amplitude detection circuit for detecting an amplitude value of a vertical or horizontal synchronizing signal in the television video signal; an amplitude control circuit for controlling an amplitude of an input television video signal; a synchronization circuit for detecting a vertical synchronizing signal and a horizontal synchronizing signal in the television video signal so as to generate various pulses including a clock pulse synchronized with the input television video signal by controlling an oscillation frequency of an oscillation circuit; and a synchronization phase lock detection circuit for detecting whether the synchronization circuit has been pulled into synchronism with the input television video signal, so that the amplitude control circuit is controlled by an output of the second amplitude detection circuit when synchronization phase-lock is established while controlled by an output of the first amplitude detection circuit when the synchronization phase-lock comes out.

摘要翻译： 公开了一种自动增益控制装置，包括：第一幅度检测电路，用于检测电视视频信号的平均振幅值，相同电视视频信号的峰值振幅值，或通过混合平均振幅值和 具有预定混合比的峰值振幅值; 第二振幅检测电路，用于检测电视视频信号中的垂直或水平同步信号的振幅值; 幅度控制电路，用于控制输入电视视频信号的幅度; 用于检测电视视频信号中的垂直同步信号和水平同步信号的同步电路，以通过控制振荡电路的振荡频率产生包括与输入电视视频信号同步的时钟脉冲的各种脉冲; 以及同步锁相检测电路，用于检测同步电路是否已被拉入与输入的电视视频信号同步，使得当建立同步锁相时，幅度控制电路由第二幅度检测电路的输出控制，而 当同步锁相出来时由第一幅度检测电路的输出控制。

公开(公告)号：US4950926A

公开(公告)日：1990-08-21

申请号：US261066

申请日：1988-10-24

申请人： Mitsuo Isobe ,  Shinich Nakauchida

发明人： Mitsuo Isobe ,  Shinich Nakauchida

IPC分类号： G11C11/41 ,  G11C11/409 ,  H01L27/10 ,  H03K19/00

CPC分类号： H03K19/0013

摘要： A control signal output circuit for outputting a control signal in response to first and second input signals and a power source voltage, comprises an inverter which inverts one of the first and second input signals and outputs an inverted signal. The control signal output circuit further comprises a logic circuit which outputs a control signal in response to the inverted signal and the other of the first and second input signals. A switch is further provided to disconnect the inverter from the power source voltage in response to the other of the first and second input signals.

摘要翻译： 用于响应于第一和第二输入信号和电源电压而输出控制信号的控制信号输出电路包括反相器，其将第一和第二输入信号之一反相并输出反相信号。 控制信号输出电路还包括逻辑电路，其响应于反相信号和第一和第二输入信号中的另一个输出控制信号。 进一步提供开关以响应于第一和第二输入信号中的另一个而断开逆变器与电源电压的连接。