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    Semiconductor memory device using partial decoders for redundancy
    2.
    发明授权
    Semiconductor memory device using partial decoders for redundancy 失效
    半导体存储器件使用部分解码器进行冗余

    公开(公告)号：US4881202A

    公开(公告)日：1989-11-14

    申请号：US138800

    申请日：1987-12-29

    申请人： Jun-ichi Tsujimoto ,  Masataka Matsui ,  Hiroshi Iwai ,  Takayuki Ohtani

    发明人： Jun-ichi Tsujimoto ,  Masataka Matsui ,  Hiroshi Iwai ,  Takayuki Ohtani

    IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/802 ,  G11C29/844

    摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.

    Static memory utilizing transition detectors to reduce power consumption
    3.
    发明授权
    Static memory utilizing transition detectors to reduce power consumption 失效
    静态存储器利用转换检测器来降低功耗

    公开(公告)号：US4744063A

    公开(公告)日：1988-05-10

    申请号：US613614

    申请日：1984-05-24

    申请人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

    发明人： Takayuki Ohtani ,  Takayasu Sakurai ,  Mitsuo Isobe ,  Tetsuya Iizuka

    IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/418 ,  G11C16/06 ,  G11C8/00

    CPC分类号： G11C11/418 ,  G11C8/18

    摘要： A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

    摘要翻译： 静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。 当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。 该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4587638A

    公开(公告)日：1986-05-06

    申请号：US630115

    申请日：1984-07-12

    申请人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

    发明人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

    IPC分类号： G11C29/00 ,  G11C7/02

    CPC分类号： G11C29/84 ,  G11C29/832

    摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

    摘要翻译： 在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。 当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。 连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。 因此，不选择具有缺陷部分的存储单元。

    Semiconductor memory device with a potential level-setting circuit
    6.
    发明授权
    Semiconductor memory device with a potential level-setting circuit 失效
    具有电位电平设定电路的半导体存储器件

    公开(公告)号：US4982365A

    公开(公告)日：1991-01-01

    申请号：US476137

    申请日：1990-02-07

    申请人： Takayuki Ohtani ,  Mitsuo Isobe

    发明人： Takayuki Ohtani ,  Mitsuo Isobe

    IPC分类号： G11C11/41 ,  G11C7/20 ,  G11C11/401 ,  G11C11/419

    CPC分类号： G11C7/20 ,  G11C11/419

    摘要： During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.

    摘要翻译： 在数据清除操作期间，在保持关断状态下，与至少一列相关联的每个静态型存储单元中的传输栅极晶体管，并入存储单元中的两个驱动晶体管中的一个的源极被设置为高 电位电平，另一个驱动晶体管的源极为低电平。 结果，在存储单元矩阵中执行清零操作至少为1列。 由于存储器件的布置，在清除操作期间不需要地址选择操作来选择存储器单元。 此外，清除操作以存储单元矩阵中的1列的最小单位进行。 因此，清除操作的处理时间减少。 此外，由于在清除动作期间存储单元中的传输栅极晶体管保持在截止状态，所以清除操作期间流过的直流电流减小，结果是功耗降低。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4882708A

    公开(公告)日：1989-11-21

    申请号：US145411

    申请日：1988-01-19

    申请人： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

    发明人： Shigeyuki Hayakawa ,  Mitsuo Isobe ,  Takayuki Ohtani

    IPC分类号： G11C11/41 ,  G11C11/419

    CPC分类号： G11C11/419

    摘要： A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.

    摘要翻译： 一方面，位线之间和另一方的电源电位之间设置预充电电路。 通过清除信号将预充电电路控制为导通/不导通。 还提供控制单元，当提供清除信号时，控制解码器，以将所有字线设置为选择状态。 在清除模式下，写入电路将同一数据同时写入所有存储单元。

    Transition detector circuit
    8.
    发明授权
    Transition detector circuit 失效
    过渡检测电路

    公开(公告)号：US4563593A

    公开(公告)日：1986-01-07

    申请号：US538277

    申请日：1983-10-03

    申请人： Mitsuo Isobe ,  Takayuki Ohtani

    发明人： Mitsuo Isobe ,  Takayuki Ohtani

    IPC分类号： H03K5/1532 ,  H03K3/02 ,  H03K5/1534 ,  H03K5/153

    CPC分类号： H03K5/1534 ,  H03K3/02

    摘要： A transition detector circuit comprises a first invertor train comprising 2n stages of invertors (n: positive integer including zero), the input thereof being connected to a signal input terminal while the output thereof is connected to an in-phase output terminal, a second invertor train comprising 2n+1 stages of invertors, the input thereof being connected to the signal input terminal, while the output thereof is connected to an antiphase output terminal, a third invertor train comprising at least one stage of an invertor, which is connected to the output of the first invertor train, a fourth invertor train, comprising at least one stage of an invertor, which is connected to the output of the second invertor train, and a fifth invertor train comprising at least one stage of an invertor, which is connected to the signal input terminal. The transition detector circuit further comprises a first switching circuit which turns on or off in response to a signal fed from the third invertor train to produce a pulse signal having a first delay time determined by the first and third invertor trains, and a second switching circuit which turns on or off in response to a signal fed from the fourth invertor train and turns off or on in response to a signal fed from the fifth invertor train to produce a pulse signal having a second delay time determined by the second, fourth and fifth invertor trains.

    摘要翻译： 一个转换检测器电路包括一个包括2n级反相器（n：包括零的正整数）的第一个反相器列，其输入连接到一个信号输入端，同时其输出连接到一个同相输出端，一个第二反相器 其包括2n + 1级的反相器，其输入连接到信号输入端，而其输出连接到反相输出端，第三反相器列，包括至少一级的反相器，其连接到反相器 第一反相器列车的输出，第四反相器列车，包括连接到第二逆变器列车的输出端的反相器的至少一级，以及包括连接到第二逆变器列的至少一级的逆变器列 到信号输入端子。 转换检测器电路还包括第一开关电路，其响应于从第三反相器序列馈送的信号而导通或截止以产生具有由第一和第三反相器列车确定的第一延迟时间的脉冲信号，以及第二开关电路 其响应于从第四反相器列车馈送的信号而接通或断开，并且响应于从第五反相器列车馈送的信号而断开或接通，以产生具有由第二，第四和第五变换器确定的第二延迟时间的脉冲信号 倒车火车

    Static memory using a MIS field effect transistor
    9.
    发明授权
    Static memory using a MIS field effect transistor 失效
    使用MIS场效应晶体管的静态存储器

    公开(公告)号：US4815040A

    公开(公告)日：1989-03-21

    申请号：US100640

    申请日：1987-09-24

    申请人： Masataka Matsui ,  Takayuki Ohtani

    发明人： Masataka Matsui ,  Takayuki Ohtani

    IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419

    摘要： In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.

    摘要翻译： 在选定的列中，不选择上拉晶体管对，而是选择传输栅极晶体管对。 在读取模式下，传输栅极晶体管对用作位线对之间的上拉负载。 然而，传输栅极晶体管对保持截止，直到位线对上的电压从电源电位电平降低到传输栅极晶体管的阈值电压电平。 因此，当位线对上的电压在等于电源电位电平的电压到低于电源电位的电位的范围内时，在位线对中不形成直流电流路径， 阈值电压电平，并且位线对上的电位差的增加速率由存储单元的引入电流决定。 因此，可以实现高速感测操作。 在写入模式下，传输栅极晶体管对用于位线上拉功能。 由于没有布置正常导通的位线负载晶体管，所以不存在包括位线对的直流电路，因此可以实现低功耗。

    Low power consumption, high speed CMOS signal input circuit
    10.
    发明授权
    Low power consumption, high speed CMOS signal input circuit 失效
    低功耗，高速CMOS信号输入电路

    公开(公告)号：US4594519A

    公开(公告)日：1986-06-10

    申请号：US534691

    申请日：1983-09-22

    申请人： Takayuki Ohtani ,  Tetsuya Iizuka

    发明人： Takayuki Ohtani ,  Tetsuya Iizuka

    IPC分类号： H03K19/20 ,  G11C8/00 ,  H03K19/00 ,  H03K19/094 ,  H03K19/003

    CPC分类号： H03K19/09425 ,  H03K19/09429

    摘要： A signal input circuit particularly well suited for use in MOS integrated circuits. The signal input circuit includes: and input gate circuit for receiving an input signal and an enable control signal, and for generating an output signal equal to the input signal when the enable control signal is in an "enable" state, and for providing a high output impedance when the enable control signal is in a "disable" state; and a holding circuit coupled to an output of the input gate circuit and to receiving the enable control signal, for holding, during the disable state, the output state of the input gate circuit immediately before the enable control signal changes to a disable state, the output impedance being high when the enable control signal is in an enable state.

    摘要翻译： 特别适用于MOS集成电路的信号输入电路。 信号输入电路包括：输入门电路，用于接收输入信号和使能控制信号，并且在使能控制信号处于“使能”状态时，产生等于输入信号的输出信号，并提供高电平 当使能控制信号处于“禁止”状态时的输出阻抗; 以及保持电路，其耦合到所述输入门电路的输出并且接收所述使能控制信号，以在所述禁止状态期间保持所述输入门电路的输出状态，所述输入门电路在所述使能控制信号变为禁用状态之前， 当使能控制信号处于使能状态时，输出阻抗为高。