发明授权
- 专利标题: Method of manufacturing a semiconductor integrated circuit device
- 专利标题(中): 制造半导体集成电路器件的方法
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申请号: US82212申请日: 1987-08-06
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公开(公告)号: US4814287A公开(公告)日: 1989-03-21
- 发明人: Toyoki Takemoto , Kenji Kawakita , Hiroyuki Sakai
- 申请人: Toyoki Takemoto , Kenji Kawakita , Hiroyuki Sakai
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co. Ltd.
- 当前专利权人: Matsushita Electric Industrial Co. Ltd.
- 当前专利权人地址: JPX Osaka
- 优先权: JPX58-181027 19830928
- 主分类号: H01L27/00
- IPC分类号: H01L27/00 ; H01L21/74 ; H01L21/762 ; H01L21/763 ; H01L21/8222 ; H01L21/8236 ; H01L27/06 ; H01L27/088 ; H01L21/76 ; H01L21/95
摘要:
A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.
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