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    Method of increasing the thickness of a field oxide
    1.
    发明授权
    Method of increasing the thickness of a field oxide 失效
    增加场氧化物厚度的方法

    公开(公告)号：US4721687A

    公开(公告)日：1988-01-26

    申请号：US11892

    申请日：1987-02-06

    申请人： Masakazu Kakumu ,  Sigeru Morita

    发明人： Masakazu Kakumu ,  Sigeru Morita

    IPC分类号： H01L21/316 ,  H01L21/70 ,  H01L21/76 ,  H01L21/762 ,  H01L21/94 ,  H01L21/95

    CPC分类号： H01L21/76213 ,  Y10S148/117

    摘要： A method of manufacturing a semiconductor substrate, and, in particular, a technique of electrically isolating a semiconductor element formed on a semiconductor substrate. The method comprises the steps of depositing a silicon oxide layer on the surface of a silicon substrate, for its protection; forming a silicon nitride layer on the silicon oxide layer; selectively eliminating the silicon nitride layer; oxidizing the silicon substrate, with the retained silicon nitride layer being used as a mask, thereby providing an oxide layer; depositing a polycrystalline silicon layer on the oxide layer and the retained acid-resisting layer; oxidizing the polycrystalline silicon layer to provide an insulation layer; eliminating the insulation layer until the silicon nitride layer is exposed; and removing all the silicon nitride layer. The method is capable of enabling the formation of a thick semiconductor element-isolating oxide layer, with a high precision, in a narrow region from which the semiconductor element is to be isolated.

    摘要翻译： 一种制造半导体衬底的方法，特别是一种将半导体衬底上形成的半导体元件电隔离的技术。 该方法包括以下步骤：在硅衬底的表面上沉积氧化硅层以进行保护; 在所述氧化硅层上形成氮化硅层; 选择性地消除氮化硅层; 氧化硅衬底，将保留的氮化硅层用作掩模，由此提供氧化物层; 在氧化物层和保留的耐酸层上沉积多晶硅层; 氧化多晶硅层以提供绝缘层; 消除绝缘层，直到暴露氮化硅层; 并去除所有的氮化硅层。 该方法能够在要分离半导体元件的窄区域中以高精度形成厚半导体元件隔离氧化物层。

    Semiconductor planarization process and structures made thereby
    2.
    发明授权
    Semiconductor planarization process and structures made thereby 失效
    由此形成的半导体平面化工艺和结构

    公开(公告)号：US4539744A

    公开(公告)日：1985-09-10

    申请号：US576665

    申请日：1983-02-03

    申请人： Greg Burton

    发明人： Greg Burton

    IPC分类号： H01L21/306 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/95

    CPC分类号： H01L21/76202 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31604

    摘要： A silicon substrate having a silicon dioxide bird's head is provided. A thermal oxide layer is grown on the exposed silicon surface. A layer, e.g., 4000 A.degree., of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide bird's head. The structure is heated to 950.degree. C., causing a reflow of the glass which results in a planar surface. The thermal oxide and the phosphogermanosilicate glass are then wet etched at the same rate with a solution of hydrofluoric acid, ammonium fluoride, and deionized water. The wet etch is terminated when the exposed silicon surface is reached, resulting in a smooth surface as defined by the planar reflow surface. Other embodiments are disclosed.

    摘要翻译： 提供具有二氧化硅鸟头的硅衬底。 在暴露的硅表面上生长热氧化物层。 在热氧化物上和二氧化硅鸟头上沉积一层例如4000的磷硅锗玻璃。 将该结构加热至950℃，引起玻璃的回流，产生平坦的表面。 然后以与氢氟酸，氟化铵和去离子水的溶液相同的速率对热氧化物和磷硅锗硅酸盐玻璃进行湿蚀刻。 当暴露的硅表面到达时，湿蚀刻终止，导致如平面回流表面所限定的光滑表面。 公开了其他实施例。

    Method of manufacturing an integrated circuit device having vertical field effect transistors
    4.
    发明授权
    Method of manufacturing an integrated circuit device having vertical field effect transistors 失效
    制造具有垂直场效应晶体管的集成电路器件的方法

    公开(公告)号：US4449284A

    公开(公告)日：1984-05-22

    申请号：US183064

    申请日：1980-09-02

    申请人： Masafumi Shimbo

    发明人： Masafumi Shimbo

    IPC分类号： H01L21/306 ,  H01L27/02 ,  H01L29/10 ,  H01L29/739 ,  H01L21/95

    CPC分类号： H01L21/30608 ,  H01L27/0225 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/739

    摘要： A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

    摘要翻译： 一种制造包括垂直静电感应晶体管（SIT）的集成电路器件的方法，所述垂直静电感应晶体管（SIT）在所述栅极区域和所述漏极（或源极）区域之间具有第一凹陷，以减小所述两个区域之间的电容和所述SIT的外表面上的第二凹陷 栅极减少栅极电容和少数载流子存储。 该方法包括以下步骤：在掩模膜位于栅极区域和漏极区域的部分处，去除SIT沟道区上的掩模膜; 在通道区域中形成第一和第二凹槽; 局部氧化暴露的通道区域; 并通过去除掩模膜形成栅区和漏区。

    Method of manufacturing a semiconductor integrated circuit device
    5.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US4814287A

    公开(公告)日：1989-03-21

    申请号：US82212

    申请日：1987-08-06

    申请人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

    发明人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

    IPC分类号： H01L27/00 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8236 ,  H01L27/06 ,  H01L27/088 ,  H01L21/76 ,  H01L21/95

    CPC分类号： H01L21/743 ,  H01L21/76245 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/7627 ,  H01L21/76281

    摘要： A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.

    摘要翻译： 一种制造双极型MOS型半导体集成电路器件的方法或者具有高集成度和高​​性能的两种类型的集成方法，其中电路包括第一器件区域，其中第一器件区域的侧表面和整个区域 有源区的下部由氧化硅制成，其第二器件区的有源区的侧表面和下部的一部分由氧化硅制成。 根据本发明，底部开放的晶体管和其底部未打开的晶体管可以自由地设置在基板上，从而将晶体管分成从基板提供电压的晶体管和晶体管 不能从基板供给电压，从而可以减少传统上需要的布线。 此外，在完全分离的这种晶体管中，完全防止与圆周的寄生效应，从而可以提供优异的特性。

    Planar void free isolation structure
    6.
    发明授权
    Planar void free isolation structure 失效
    平面无空隙隔离结构

    公开(公告)号：US4680614A

    公开(公告)日：1987-07-14

    申请号：US711554

    申请日：1985-03-14

    申请人： Klaus D. Beyer ,  Victor J. Silvestri

    发明人： Klaus D. Beyer ,  Victor J. Silvestri

    IPC分类号： H01L21/20 ,  H01L21/74 ,  H01L21/763 ,  H01L21/95 ,  H01L27/04

    CPC分类号： H01L21/743 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S148/131

    摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

    摘要翻译： 描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。 隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。 第一绝缘层位于沟槽的侧壁上。 沟槽的底部或底部对单晶半导体体是开放的。 从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。 沟槽宽度x的优选范围为约10微米或更小。 多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。 第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。 密封的外延单晶半导体防止在沟槽图案内形成空隙。 外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

    Method for manufacturing a field isolation structure for a semiconductor device
    10.
    发明授权
    Method for manufacturing a field isolation structure for a semiconductor device 失效
    半导体装置的场隔离结构的制造方法

    公开(公告)号：US4404735A

    公开(公告)日：1983-09-20

    申请号：US263280

    申请日：1981-05-13

    申请人： Junji Sakurai

    发明人： Junji Sakurai

    IPC分类号： H01L21/268 ,  H01L21/31 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L21/95

    CPC分类号： H01L21/268 ,  H01L21/32115 ,  H01L21/76 ,  H01L21/76224

    摘要： A method for forming a field isolation structure for a semiconductor device, in which a groove is formed in a semiconductor substrate, an insulating layer is formed on the substrate at least in the groove, a glass layer or a silicon layer is formed thereon, and thereafter a high energy beam such as a laser beam is irradiated onto the glass or silicon layer to selectively heat the same thereby to melt or fluidify the layer and let the same flow into the groove is disclosed. A smooth and flat surface is obtained through the above melting process, which also prevents electrical breaks in wiring layers formed thereon. The method is particularly suited to producing small field isolation structures thus improving the integration density of the device.

    摘要翻译： 一种用于形成半导体器件的场隔离结构的方法，其中在半导体衬底中形成沟槽，至少在沟槽中在衬底上形成绝缘层，在其上形成玻璃层或硅层， 此后，将诸如激光束的高能量光束照射到玻璃或硅层上以选择性地加热玻璃或硅层，从而熔化或流化该层，并且使相同的流入凹槽。 通过上述熔融工艺获得光滑平坦的表面，这也防止了在其上形成的布线层中的电断裂。 该方法特别适用于生产小型场隔离结构，从而提高了器件的集成密度。