发明授权
- 专利标题: Memory device with improved common data line bias arrangement
- 专利标题(中): 具有改进的公共数据线偏置布置的存储器件
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申请号: US108623申请日: 1987-10-15
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公开(公告)号: US4829479A公开(公告)日: 1989-05-09
- 发明人: Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
- 申请人: Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX59-121820 19840615
- 主分类号: G11C11/417
- IPC分类号: G11C11/417 ; G11C7/10
摘要:
A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
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