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    High speed BI CMOS logic circuit and a semiconductor integrated circuit device using same
    3.
    发明授权
    High speed BI CMOS logic circuit and a semiconductor integrated circuit device using same 失效
    高速BI CMOS逻辑电路和使用其的半导体集成电路器件

    公开(公告)号：US5296755A

    公开(公告)日：1994-03-22

    申请号：US799327

    申请日：1991-11-27

    Applicant: Kazuhisa Miyamoto ,  Mitsugu Kusunoki ,  Masanori Odaka ,  Mitsuo Usami

    Inventor： Kazuhisa Miyamoto ,  Mitsugu Kusunoki ,  Masanori Odaka ,  Mitsuo Usami

    IPC: H01L27/06 ,  G11C11/418 ,  H01L21/8249 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K17/04

    CPC classification number: H03K19/09448 ,  G11C11/418 ,  H03K19/013

    Abstract: Herein disclosed is a logic circuit which has an input bipolar transistor for receiving an input signal at its base; variable impedance circuit having at least a first P-channel MOSFET connected between a first supply voltage and the collector of the input bipolar transistor; a second N-channel MOSFET connected between the emitter of the input bipolar transistor and a second supply voltage; an output bipolar transistor connected between the first supply voltage and the output terminal of the circuit for receiving the collector potential of the input bipolar transistor at its base; and a third, pull-down MOSFET connected between the output terminal and the second or third supply voltage.

    Abstract translation: 这里公开了一种逻辑电路，其具有用于在其基极处接收输入信号的输入双极晶体管; 可变阻抗电路具有连接在第一电源电压和输入双极晶体管的集电极之间的至少第一P沟道MOSFET; 连接在输入双极晶体管的发射极和第二电源电压之间的第二N沟道MOSFET; 连接在电路的第一电源电压和输出端之间的输出双极晶体管，用于接收输入双极晶体管的基极的集电极电位; 以及连接在输出端子和第二或第三电源电压之间的第三个下拉MOSFET。

    Semiconductor integrated circuit with bipolar transistors and MOSFETs
    4.
    发明授权
    Semiconductor integrated circuit with bipolar transistors and MOSFETs 失效
    具有双极晶体管和MOSFET的半导体集成电路

    公开(公告)号：US5220187A

    公开(公告)日：1993-06-15

    申请号：US917907

    申请日：1992-07-21

    Applicant: Shuuichi Miyaoka ,  Masanori Odaka ,  Katsumi Ogiue

    Inventor： Shuuichi Miyaoka ,  Masanori Odaka ,  Katsumi Ogiue

    IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0944 ,  H03K19/173

    CPC classification number: H03K19/09448 ,  H01L27/11896

    Abstract: A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5140550A

    公开(公告)日：1992-08-18

    申请号：US591883

    申请日：1990-10-02

    Applicant: Shuuichi Miyaoka ,  Masanori Odaka ,  Hiroshi Higuchi ,  Toshikazu Arai

    Inventor： Shuuichi Miyaoka ,  Masanori Odaka ,  Hiroshi Higuchi ,  Toshikazu Arai

    IPC: G11C8/10 ,  G11C8/14

    CPC classification number: G11C8/10 ,  G11C8/14

    Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

    Abstract translation: 提供一种半导体存储器件，其包括多个存储器阵列，每个存储器阵列包括主字线，连接有多个存储器单元的子字线，以及选择性地将子字线连接到主字线的解码器。 主字线相对较短，因为它们在存储器阵列之间是电隔离的，因此它们的电阻可以相对较低。 主字线不与多个存储单元直接连接，这导致与通常情况下的主字线相比较较小的电容。 因此，半导体存储器件可以具有增强的操作速度。

    Semiconductor integrated circuit device
    7.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4879681A

    公开(公告)日：1989-11-07

    申请号：US293760

    申请日：1989-01-05

    Applicant: Hideo Miwa ,  Kazuhiro Tsuruoka ,  Koudou Yamauchi ,  Hitoshi Endoh ,  Masanori Odaka

    Inventor： Hideo Miwa ,  Kazuhiro Tsuruoka ,  Koudou Yamauchi ,  Hitoshi Endoh ,  Masanori Odaka

    IPC: G11C11/414 ,  G11C7/10 ,  G11C8/06 ,  H01L27/10 ,  H03K19/003

    CPC classification number: G11C7/109 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C8/06

    Abstract: A semiconductor memory device includes an input circuit and an output circuit. To prevent the erroneous operation of the input circuit by the noise which develops at the time of the change of the output signal of the output circuit, the threshold voltage of the input circuit is changed, or an internal signal generated by the internal circuit is fixed to a predetermined level. In an output circuit having a tri-state output function, the threshold voltage of the input circuit is changed when the output is brought into the high impedance state, or the internal signal generated by the input circuit is fixed to a predetermined state. Using these arrangements it is possible to prevent the erroneous operation of the input circuit by the noise occurring when the output is brought into the high impedance state. Furthermore, in an output circuit having a tri-state output function, the threshold voltage of the input circuit is changed when the output signal of the output circuit is brought into the high impedance state, too, when the output signal changes. This makes it possible to prevent an erroneous detection of the level of the input signal which might otherwise be caused by the noise.

    Abstract translation: 半导体存储器件包括输入电路和输出电路。 为了防止在输出电路的输出信号变化时产生的噪声导致输入电路的错误操作，输入电路的阈值电压发生变化，或由内部电路产生的内部信号固定 达到预定水平。 在具有三态输出功能的输出电路中，输入电路的阈值电压在输入为高阻态的情况下变化，或将输入电路产生的内部信号固定为规定状态。 利用这些配置，可以防止当输出为高阻抗状态时出现的噪声对输入电路的错误操作。 此外，在具有三态输出功能的输出电路中，当输出信号变化时，当输出电路的输出信号进入高阻抗状态时，输入电路的阈值电压也改变。 这使得可以防止可能由噪声引起的输入信号的电平的错误检测。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4748487A

    公开(公告)日：1988-05-31

    申请号：US053479

    申请日：1987-05-26

    Applicant: Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

    Inventor： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

    IPC: H01L21/8238 ,  G11C11/34 ,  G11C11/419 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02

    CPC classification number: G11C11/419 ,  H01L27/11

    Abstract: A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

    Abstract translation: 一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET（Qp，Qp）和在互补数据线D和上拉和下降D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，两个MISFET的形成是 相同的形状。 此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。 换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals
    9.
    发明授权
    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
    半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作

    公开(公告)号：US5457412A

    公开(公告)日：1995-10-10

    申请号：US149935

    申请日：1993-11-10

    Applicant: Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    Inventor： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    IPC: G11C11/413 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/0175 ,  H03K19/08

    CPC classification number: H03K19/017527

    Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

    Abstract translation: 提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。 输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和 电路。 该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。 由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

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