发明授权
- 专利标题： Apparatus for performing floating point arithmetic operations and rounding the result thereof
- 专利标题（中）： 用于执行浮点算术运算并舍入其结果的装置
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申请号： US838941申请日： 1986-03-12
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公开(公告)号： US4839846A公开(公告)日： 1989-06-13
- 发明人: Kenji Hirose , Tadaaki Bandoh , Hidekazu Matsumoto , Shinichiro Yamaguchi , Hirokazu Hirayama , Hiroaki Nakanishi
- 申请人： Kenji Hirose , Tadaaki Bandoh , Hidekazu Matsumoto , Shinichiro Yamaguchi , Hirokazu Hirayama , Hiroaki Nakanishi
- 申请人地址： JPX Tokyo JPX Tokyo
- 专利权人： Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人： Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人地址： JPX Tokyo JPX Tokyo
- 优先权： JPX60-53975 19850318
- 主分类号： G06F7/00
- IPC分类号： G06F7/00 ; G06F7/38 ; G06F7/485 ; G06F7/50 ; G06F7/508 ; G06F7/76
摘要：
An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).
公开/授权文献
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