公开(公告)号：US5841963A

公开(公告)日：1998-11-24

申请号：US861471

申请日：1997-05-21

申请人： Tetsuaki Nakamikawa ,  Shin Kokura ,  Kenichi Kurosawa ,  Shinichiro Yamaguchi ,  Yoshihiro Miyazaki ,  Hiroshi Ohguro

发明人： Tetsuaki Nakamikawa ,  Shin Kokura ,  Kenichi Kurosawa ,  Shinichiro Yamaguchi ,  Yoshihiro Miyazaki ,  Hiroshi Ohguro

IPC分类号： G06F11/16 ,  G06F15/17

CPC分类号： G06F11/1658

摘要： A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.

摘要翻译： 由由多个数据传送单元连接的两个计算机系统和用于存储器副本的多个数据传送通道组成的双计算机系统，使得在从故障恢复时再次同步计算机系统。 当数据传输通道没有发生故障时，数据传输单元在存储器复制操作中共享数据传输的负载，并且当在存储器复制操作期间在任何数据传送单元发生故障时，使用剩余的正常数据传送单元 再次传送数据，从而高速地进行存储器复制，以便在从故障恢复时再次同步计算机系统，并且提高从故障恢复时的系统可靠性。

公开(公告)号：US5003458A

公开(公告)日：1991-03-26

申请号：US111618

申请日：1987-10-23

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC分类号： G06F11/14

CPC分类号： G06F11/141

摘要： Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

摘要翻译： 在微程序控制数据处理装置中进行指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

公开(公告)号：US4839846A

公开(公告)日：1989-06-13

申请号：US838941

申请日：1986-03-12

申请人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

发明人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/485 ,  G06F7/50 ,  G06F7/508 ,  G06F7/76

CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49957

摘要： An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

摘要翻译： 能够在浮点运算中高速进行圆形处理的运算部。 提供一种用于在一个代表全局的输出中表示全部1的信号和表示四舍五入的信号，进位查找电路和用于产生圆形精度信号的电路的条件下检测溢出的电路。 当溢出发生时，尾数产生为“1”。 操作单元兼容电气和电子工程师协会（IEEE）推荐的单，双和扩展精度。

公开(公告)号：US4811269A

公开(公告)日：1989-03-07

申请号：US916695

申请日：1986-10-08

申请人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

发明人： Kenji Hirose ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Shinichiro Yamaguchi ,  Hirokazu Hirayama ,  Hiroaki Nakanishi

IPC分类号： G06F7/487 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53

CPC分类号： G06F7/5324 ,  G06F2207/3896

摘要： A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.

摘要翻译： 一个用于切片乘法器的位片倍增电路，为分片乘法器产生乘积，并对乘积求和，得到乘法结果。 该电路包括一个限幅单元，用于对被乘数进行分片，对应的乘法单元数目与分片被乘数的数目相对应，并且与乘法单元对应地设置的加法单位，并对相应的乘法单元进行相乘结果的求和， 通过乘法单元在分片乘法器和被乘数的乘法运算中被乘数，乘法结果是通过将由加法单元产生的所有求和结果求和来获得的。

公开(公告)号：US5146569A

公开(公告)日：1992-09-08

申请号：US674398

申请日：1991-03-25

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Morioka Takayuki ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Morioka Takayuki ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC分类号： G06F11/14

CPC分类号： G06F11/141

摘要： Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

摘要翻译： 微程序控制数据处理装置中的指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

公开(公告)号：US4841439A

公开(公告)日：1989-06-20

申请号：US917974

申请日：1986-10-14

申请人： Atsuhiko Nishikawa ,  Yoshihiro Miyazaki ,  Masayuki Tanji ,  Soichi Takaya ,  Shinichiro Yamaguchi

发明人： Atsuhiko Nishikawa ,  Yoshihiro Miyazaki ,  Masayuki Tanji ,  Soichi Takaya ,  Shinichiro Yamaguchi

IPC分类号： G06F12/10 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3861 ,  G06F9/268

摘要： The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.

摘要翻译： 本申请涉及一种用于重新启动由于页面故障而中断的指令的执行的方法。 当在执行指令期间出现页面错误时，相关页面从外部存储器加载到主存储器中，然后再次执行引起页面错误的访问。 在执行页面错误访问的微程序的N个步骤之后，启动页面异常处理，并且在微程序计数器的内容的保存/恢复操作时，微程序的内容减少N，从而重新启动执行 从执行页面错误访问的微程序步骤开始的指令。

公开(公告)号：US6032265A

公开(公告)日：2000-02-29

申请号：US682956

申请日：1996-07-18

申请人： Hiroshi Oguro ,  Shinichiro Yamaguchi ,  Yoshihiro Miyazaki ,  Soichi Takaya ,  Masataka Hiramatsu ,  Nobuo Akeura

发明人： Hiroshi Oguro ,  Shinichiro Yamaguchi ,  Yoshihiro Miyazaki ,  Soichi Takaya ,  Masataka Hiramatsu ,  Nobuo Akeura

IPC分类号： G06F11/00 ,  G06F11/16 ,  G06F11/20 ,  G06F11/30 ,  G06F13/00 ,  G06F15/16

CPC分类号： G06F11/2056 ,  G06F11/2017 ,  G06F11/2046 ,  G06F11/004 ,  G06F11/16 ,  G06F11/1604 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/20 ,  G06F11/2005 ,  G06F11/2089

摘要： A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.

摘要翻译： 容错计算机系统在使用替代I / O块来继续处理时防止I / O故障到达CPU块，使用具有最少专用外设电路的常用通用处理器。 双系统总线适配器不在快速操作的CPU部分提供，需要复杂的封装技术，而是在CPU和I / O总线适配器之间的低速接口中。 这允许CPU和I / O总线适配器在实现容错计算机系统的同时由普通数据处理器，工作站或个人计算机共享。 如果在CPU或I / O总线适配器中出现单触发硬件故障，故障组件与系统断开连接，系统将不间断地运行。

公开(公告)号：US5852728A

公开(公告)日：1998-12-22

申请号：US585344

申请日：1996-01-11

申请人： Koji Matsuda ,  Soichi Takaya ,  Yoshihiro Miyazaki ,  Kenichi Kurosawa ,  Shinichiro Yamaguchi ,  Sako Ishikawa ,  Akira Yamagiwa ,  Masao Inoue ,  Kenji Kashiwagi

发明人： Koji Matsuda ,  Soichi Takaya ,  Yoshihiro Miyazaki ,  Kenichi Kurosawa ,  Shinichiro Yamaguchi ,  Sako Ishikawa ,  Akira Yamagiwa ,  Masao Inoue ,  Kenji Kashiwagi

IPC分类号： G06F1/04 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F1/06

CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F11/1679 ,  G06F11/20

摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

摘要翻译： 本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。 在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此 在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。 设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。

公开(公告)号：US5737513A

公开(公告)日：1998-04-07

申请号：US650662

申请日：1996-05-20

申请人： Koji Matsuda ,  Yoshihiro Miyazaki ,  Soichi Takaya ,  Kazuhiro Hyuga ,  Nobuo Akeura ,  Shinichiro Yamaguchi ,  Naoto Miyazaki ,  Satoru Kayukawa

发明人： Koji Matsuda ,  Yoshihiro Miyazaki ,  Soichi Takaya ,  Kazuhiro Hyuga ,  Nobuo Akeura ,  Shinichiro Yamaguchi ,  Naoto Miyazaki ,  Satoru Kayukawa

IPC分类号： G06F15/16 ,  G06F11/16 ,  G06F15/177 ,  G06F11/22

CPC分类号： G06F11/1633 ,  G06F11/1645

摘要： A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.

摘要翻译： 一种在双CPU计算机中采用的双CPU计算机中维护/更换双CPU的操作兼容性的方法，其中在在线维护/更换工作期间可能错误地安装了具有初始故障的替换CPU及其系统，其中， 由于在由计算机执行的双子系统同步操作期间由于替换CPU的初始故障而导致的方法和系统的故障可以被防止在两个子系统上引起系统故障。

公开(公告)号：US4764869A

公开(公告)日：1988-08-16

申请号：US900987

申请日：1986-08-27

申请人： Yoshihiro Miyazaki ,  Soichi Takaya ,  Masayuki Tanji ,  Atsuhiko Nishikawa ,  Shinichiro Yamaguchi

发明人： Yoshihiro Miyazaki ,  Soichi Takaya ,  Masayuki Tanji ,  Atsuhiko Nishikawa ,  Shinichiro Yamaguchi

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4812

摘要： Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.

摘要翻译： 用于控制处理器中断的方法和装置。 当在执行指令的过程中检测到具有比当前程序级别更高的优先级的外部中断请求时，处理被中断，并且发出间歇中断。 在该中断中程序电平被固定，使得在中断目的地处理中断请求作为正常的中断请求，并且在中断处理之后的第二个返回指令处理从中断点恢复。