In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.