公开(公告)号：US4858165A

公开(公告)日：1989-08-15

申请号：US64835

申请日：1987-06-19

申请人： Paul E. Gronowski ,  Victor Peng ,  Nachum M. Gavrielov

发明人： Paul E. Gronowski ,  Victor Peng ,  Nachum M. Gavrielov

IPC分类号： G06F7/485 ,  G06F7/50

CPC分类号： G06F7/485 ,  G06F2207/5442

摘要： The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. In the performance of the effective subtraction operation, the determination of absolute value of the difference between the operand exponent arguments must be obtained in order to determine the correct procedure. In the present invention, a difference between a subset of the operand exponent arguments is calculated and the result of this calculation is used to anticipate the correct procedure. By careful selection of the anticipated correct procedure, when the selection is erroneous, the correct result is immediately available. The availabilty of the correct result is achieved by selecting the subset of operand exponent arguments so that, in the event that the result is erroneous, the correct difference is such that the associated operand fraction (i.e., to be shifted by the amount of the difference) is shifted completely out of the operand fraction field (stored in a register).

公开(公告)号：US4864527A

公开(公告)日：1989-09-05

申请号：US88392

申请日：1987-08-24

申请人： Victor Peng ,  William J. Bowhill ,  Nachum M. Gavrielov

发明人： Victor Peng ,  William J. Bowhill ,  Nachum M. Gavrielov

IPC分类号： G06F7/485 ,  G06F7/00 ,  G06F7/50 ,  G06F7/506 ,  G06F7/74

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49952

摘要： In a floating point addition or subtraction procedure two shift operations of the operand fraction may be required. The first shift operation, based on the difference between the operand exponent arguments, involves aligning one of the operand arguments so that the addition or subtraction procedure between the operand fractions can be performed. In order to complete the associated computations correctly, it is necessary to know if any of the fraction positions removed from the fraction by the shift operation include non-zero signals, i.e., the operation typically referred to as computation of the "sticky" bit. The second important shift operation occurs after the addition or subtraction of the operand fractions has taken place. The interim resulting operand fraction must be normalized, i.e., a non-zero signal is placed in the most significant operand fraction bit position and the operand exponent argument adjusted accordingly. In order to accomplish this normalization, the position of the leading one (most significant non-zero) bit must be identified. The present invention utilizes a carry chain both for computing the "sticky" bit information and for detecting the leading one in an operand fraction.

摘要翻译： 在浮点加法或减法程序中，可能需要操作数分数的两个移位操作。 基于操作数指数参数之间的差异的第一移位操作涉及对准操作数参数之一，使得可以执行操作数分数之间的加法或减法程序。 为了正确地完成相关联的计算，有必要知道通过移位操作从分数中删除的任何分数位置是否包括非零信号，即通常称为“粘性”位的计算的操作。 第二个重要的移位操作发生在操作数分数的加法或减法发生之后。 中间产生的操作数分数必须被归一化，即非零信号被置于最高有效的操作数分数位位置，并且相应地调整操作数指数参数。 为了实现这种归一化，必须识别前导（最重要的非零）位的位置。 本发明利用进位链来计算“粘性”比特信息并检测操作数分数中的前导比特信息。

公开(公告)号：US07094039B2

公开(公告)日：2006-08-22

申请号：US10442123

申请日：2003-05-21

申请人： Kenny Hu ,  Victor Peng

发明人： Kenny Hu ,  Victor Peng

IPC分类号： F04B17/03

CPC分类号： F04D29/0566 ,  F04D29/023 ,  F04D29/057 ,  F05D2260/95 ,  F05D2260/96 ,  F05D2300/171 ,  F05D2300/20

摘要： A heat-dissipating fan of the invention has an axle, a bearing, a rotor and a stator. The axle and the bearing are made of a ceramic material, and are located at a central location of the rotor and the stator. The bearing is a hollow cylinder integrally formed into a single body, and has a central hole and a recess at its bottom. The axle penetrates through the central hole of the bearing to contact the recess. A magnetic force center of the silicon steel sheet is at a level lower than that of the magnetic bar to generate radial and axial force components, allowing stable rotation of the rotor. The heat-dissipating fan of the invention provides advantages such as low friction, lower noise, low energy consumption, high performance and high stability.

摘要翻译： 本发明的散热风扇具有轴，轴承，转子和定子。 轴和轴承由陶瓷材料制成，并且位于转子和定子的中心位置。 轴承是一体地形成为单体的中空圆筒，并且在其底部具有中心孔和凹部。 轴穿过轴承的中心孔与凹槽接触。 硅钢板的磁力中心处于比磁棒低的位置，以产生径向和轴向力分量，允许转子的稳定旋转。 本发明的散热风扇具有低摩擦，低噪音，低能耗，高性能，高稳定性等优点。

公开(公告)号：US4849923A

公开(公告)日：1989-07-18

申请号：US879337

申请日：1986-06-27

申请人： Sridhar Samudrala ,  Victor Peng ,  Nachum M. Gavrielov

发明人： Sridhar Samudrala ,  Victor Peng ,  Nachum M. Gavrielov

IPC分类号： G06F7/57

CPC分类号： G06F7/483 ,  G06F7/49915 ,  G06F7/49936 ,  G06F7/49947

摘要： In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.

摘要翻译： 在浮点算术执行单元中，附加加法器单元和选择网络被添加到通常执行算术浮点函数的装置中。 附加装置允许并行执行形成算术运算的一部分的某些过程。 对于所选的算术运算，最终结果可以是通常与中间移位操作相关的两个值之一。 通过并行执行处理并选择适当的结果，与串行实现中的处理的执行相比，可以减少执行时间。 使用所公开的附加装置，加法，减法，乘法和除法的基本算术运算各自可以使执行时间减少。

公开(公告)号：US4862405A

公开(公告)日：1989-08-29

申请号：US68262

申请日：1987-06-30

申请人： Bradley J. Benschneider ,  Victor Peng

发明人： Bradley J. Benschneider ,  Victor Peng

IPC分类号： G06F7/533 ,  G06F7/508 ,  G06F7/52

CPC分类号： G06F7/5312

摘要： In a multiplier unit implemented with carry/save adder stages and executing a modified Booth algorithm, the signals, required to complete the 2's complement in order to perform a subtraction operation during the multiplication procedure using carry/save adder cells, are entered in the first carry/save stage in the appropriate carry/save cell positions. In this manner, one less signal is processed by the time-critical least significant cell associated with each carry/save adder stage, thereby reducing the overall time delay associated with the multiplier unit and accelerating the multiplication operation.