公开(公告)号：US09141386B2

公开(公告)日：2015-09-22

申请号：US12890485

申请日：2010-09-24

申请人： Jeff Wiedemeier ,  Sridhar Samudrala ,  Roger Golliver

发明人： Jeff Wiedemeier ,  Sridhar Samudrala ,  Roger Golliver

IPC分类号： G06F9/305 ,  G06F9/30 ,  G06F15/76 ,  G06F9/06 ,  G06F7/00

CPC分类号： G06F9/30029 ,  G06F7/00 ,  G06F9/06 ,  G06F9/30032 ,  G06F9/30036 ,  G06F15/76

摘要： A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.

摘要翻译： 描述半导体处理器。 半导体处理器包括执行逻辑减少指令的逻辑电路。 逻辑电路具有旋转矢量元件的旋转电路，以便形成旋转矢量。 逻辑电路还具有矢量逻辑电路，用于对所述矢量和所述旋转矢量执行矢量逻辑运算。

公开(公告)号：US20140006467A1

公开(公告)日：2014-01-02

申请号：US13539198

申请日：2012-06-29

申请人： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

发明人： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

IPC分类号： G06F7/44 ,  G06F7/42

CPC分类号： G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

摘要翻译： 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

公开(公告)号：US06564239B2

公开(公告)日：2003-05-13

申请号：US10016902

申请日：2001-12-14

申请人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： G06F738

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

摘要翻译： 呈现用于执行产生根或商的平方根或除法运算的计算机方法和装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。

公开(公告)号：US20210144094A1

公开(公告)日：2021-05-13

申请号：US17093394

申请日：2020-11-09

申请人： Namrata Limaye ,  P. Venkata Suresh Kumar ,  Sridhar Samudrala ,  Kiran Patil

发明人： Namrata Limaye ,  P. Venkata Suresh Kumar ,  Sridhar Samudrala ,  Kiran Patil

IPC分类号： H04L12/803 ,  H04L12/801 ,  H04L12/815 ,  H04L12/851

摘要： Methods and apparatus for extending OpenvSwitch (OVS) megaflow offloads to hardware to address hardware pipeline limitations. Under a method implemented on a compute platform including a Network Interface Controller (NIC) having one or more ports and running software including OVS software and a Linux operating system having a kernel including a TC-flower module and a NIC driver a new megaflow is created with a mask in the OVS software employing a subset of microflow fields for a packet. The microflow fields and the megaflow mask is sent to the NIC driver. A new megaflow is implemented in the NIC driver employing a subset of the microflow fields and the NIC driver creates a new hardware flow on the NIC employing a packet match scheme using all the microflow fields. The NIC also programs a NIC hardware pipeline with the new hardware flow using a match scheme that may depend on the available hardware resources, such as the size of a TCAM.

公开(公告)号：US09213523B2

公开(公告)日：2015-12-15

申请号：US13539198

申请日：2012-06-29

申请人： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

发明人： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

IPC分类号： G06F7/38 ,  G06F7/483 ,  G06F7/544

CPC分类号： G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

摘要翻译： 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

公开(公告)号：US20090316581A1

公开(公告)日：2009-12-24

申请号：US12144975

申请日：2008-06-24

申请人： Vivek Kashyap ,  Sridhar Samudrala ,  David L. Stevens, JR.

发明人： Vivek Kashyap ,  Sridhar Samudrala ,  David L. Stevens, JR.

IPC分类号： G08C15/00

CPC分类号： H04L47/10 ,  H04L43/0811 ,  H04L45/28 ,  H04L47/12

摘要： Methods, systems and computer program products for dynamic selection and switching of TCP congestion control algorithms over a TCP connection. Exemplary embodiments include a TCP congestion control algorithm management method, including establishing a first TCP connection on a first network having an end point, wherein the TCP connection includes a first TCP congestion control algorithm, monitoring path characteristics of the TCP connection and dynamically selecting and switching to a second TCP congestion control algorithm in a response to a change in the path characteristics of the TCP connection.

摘要翻译： 通过TCP连接动态选择和切换TCP拥塞控制算法的方法，系统和计算机程序产品。 示例性实施例包括TCP拥塞控制算法管理方法，包括在具有终点的第一网络上建立第一TCP连接，其中TCP连接包括第一TCP拥塞控制算法，TCP连接的监视路径特性以及动态选择和切换 以响应于TCP连接的路径特性的变化而发送到第二TCP拥塞控制算法。

公开(公告)号：US06779012B2

公开(公告)日：2004-08-17

申请号：US10419454

申请日：2003-04-18

申请人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： G06F7552

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

摘要翻译： 用于执行产生根或商的平方根或除法运算的计算机方法和装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。

公开(公告)号：US06360241B1

公开(公告)日：2002-03-19

申请号：US09294597

申请日：1999-04-20

申请人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

发明人： Mark D. Matson ,  Robert J. Dupcak ,  Jonathan D. Krause ,  Sridhar Samudrala

IPC分类号： B06F700

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/5525 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

摘要翻译： 本发明提供用于执行产生根或商的平方根或除法运算的计算机装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。

公开(公告)号：US6144228A

公开(公告)日：2000-11-07

申请号：US340774

申请日：1999-06-28

申请人： Mark D. Matson ,  Sridhar Samudrala ,  Robert J. Dupcak

发明人： Mark D. Matson ,  Sridhar Samudrala ,  Robert J. Dupcak

IPC分类号： G06F7/48 ,  G06F7/50 ,  G06F7/52 ,  G06F7/535 ,  H03K19/0948

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F7/508 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/384 ,  G06F2207/5352

摘要： A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.

摘要翻译： 提出了一种方法和装置，用于有效地实现产生一组相互排斥的输出信号的逻辑和算术功能。 这种逻辑系列包括实现所需逻辑功能的NMOS晶体管网络。 耦合到该网络是用于提供逻辑电平恢复并用于补偿由于NMOS晶体管的任何电压降的最小数量的PMOS器件。 通过这样的结构，提高了逻辑功能的速度，面积和功耗特性。

公开(公告)号：US4852039A

公开(公告)日：1989-07-25

申请号：US64836

申请日：1987-06-19

申请人： Vijay Maheshwari ,  Sridhar Samudrala ,  Nachum M. Gavrielov

发明人： Vijay Maheshwari ,  Sridhar Samudrala ,  Nachum M. Gavrielov

IPC分类号： G06F7/485 ,  G06F7/50

CPC分类号： G06F7/485 ,  G06F2207/5442 ,  G06F7/49936 ,  G06F7/49947

摘要： The arithmetic operations performed for floating point format numbers involve procedures having a multiplicity of major steps. The effective subtraction operation can be accelerated by using two methods of execution depending on whether the absolute value of the difference between the arguments of the exponents, ABS{DELTA(E)} is .ltoreq.1 or >1. The procedure for ABS{DELTA(E)}.ltoreq.1 requires more major process steps than the situation where ABS{DELTA(E)}.ltoreq.1. To accelerate only the procedure having more major process steps, the two least significant bits of both exponent arguments are examined and based on the examination, the lengthier procedure can be initiated in parallel with the process step determining the value of ABS{DELTA(E)}. When the lengthier procedure is determined to be inappropriate based on the determined value, the results of the lengthier process can be discarded. Otherwise, the lengthier process, already in progress, is continued.