A process for forming electrical interconnect on MOS semiconductor integrated circuits includes the formation of a capping layer of oxide over the first level poly layer prior to patterning. The capping layer is then removed over selected regions. The conductive layer and capping oxide layer are then patterned to form transistor gates and interconnect. Source/drain regions are formed in active areas of the integrated circuit, and sidewall oxide is formed next to the patterned gate regions. When a second layer of interconnect is formed and patterned over the integrated circuit, contact between the first and second interconnect layers is made in the previously defined selected regions.