公开(公告)号：US06429144B1

公开(公告)日：2002-08-06

申请号：US09473451

申请日：1999-12-28

Applicant: Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

Inventor： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC: H01L21302

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/28211 ,  H01L21/28238

Abstract: In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

Abstract translation: 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。

公开(公告)号：US5789795A

公开(公告)日：1998-08-04

申请号：US579824

申请日：1995-12-28

Applicant: Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

Inventor： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

Abstract translation: 具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。 反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。 当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。 还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。 此外，还提供了设置在金属间氧化物层上方的金属二层。 在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。

公开(公告)号：US5753540A

公开(公告)日：1998-05-19

申请号：US699867

申请日：1996-08-20

Applicant: Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: H01L23/525 ,  H01L21/82

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

Abstract translation: 公开了一种用于编程反熔丝结构的方法。 反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。 由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

公开(公告)号：US5256895A

公开(公告)日：1993-10-26

申请号：US863519

申请日：1992-03-31

Applicant: Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

Inventor： Frank R. Bryant ,  Yu-Pin Han ,  Fu-Tai Liou

IPC: H01L21/32 ,  H01L21/762 ,  H01L27/12 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/32 ,  H01L21/76205

Abstract: Field oxide regions are formed between drive regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

Abstract translation: 通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的驱动区之间的场氧化物区域，打开这些层以暴露硅衬底的一部分，去除暴露的衬底的一层， 在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间​​的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。 在如图1所示的那些场地氧化物埋在衬底中的那些结构中。 如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

公开(公告)号：US5847465A

公开(公告)日：1998-12-08

申请号：US436165

申请日：1995-05-08

Applicant: Fu-Tai Liou ,  Yu-Pin Han

Inventor： Fu-Tai Liou ,  Yu-Pin Han

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L29/6659 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/76804 ,  H01L29/41775 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/90

Abstract: A method for fabrication of metal to semiconductor contacts results in sloped sidewalls in contact regions. An oxide layer is deposited and etched back to form sidewall spacers. A glass layer is then deposited and heated to reflow. After reflow, an etch back of the glass layer results is sloped sidewalls at contact openings and over steps.

Abstract translation: 金属对半导体接触的制造方法导致接触区域的倾斜侧壁。 沉积氧化物层并回蚀刻以形成侧壁间隔物。 然后沉积玻璃层并加热回流。 在回流之后，玻璃层的回蚀是在接触开口和过度台阶上的倾斜侧壁。

公开(公告)号：US5821558A

公开(公告)日：1998-10-13

申请号：US792791

申请日：1997-02-03

Applicant: Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

Inventor： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/04 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L27/112

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract translation: 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5793640A

公开(公告)日：1998-08-11

申请号：US773171

申请日：1996-12-26

Applicant: Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: G01R27/26 ,  G01R27/00

CPC classification number: G01R27/2605

Abstract: A computer-aided method and system are provided for obtaining a measurement of the capacitance value of a device under test (DUT). The complex impedance of a device under test (DUT) is measured at two nearby frequencies using an RLC meter. The two complex impedance values are then stored in a computer readable medium. The DUT is modeled by a programmed computer as a four element RLC model circuit including a resistor and inductor in series with a parallel RC circuit having a single capacitor which represents the capacitance of the DUT. Four equations which describe the electrical characteristics of the four element RLC model circuit are stored in a computer readable medium. The four measured values of complex impedance are substituted by the computer into the four stored equations. Values are obtained for the four individual RLC circuit elements by solving the four equations. The four unknown values are obtained by use of an optimization routine and then stored to a computer readable medium. The value capacitor element representing the capacitance of the DUT is then displayed.

Abstract translation: 提供了一种计算机辅助方法和系统，用于获得待测器件（DUT）的电容值的测量。 被测设备（DUT）的复阻抗使用RLC仪在两个附近的频率下测量。 然后将两个复阻抗值存储在计算机可读介质中。 DUT被编程的计算机建模为四元件RLC模型电路，其包括与表示DUT的电容的单个电容器的并联RC电路串联的电阻器和电感器。 描述四元素RLC模型电路的电特性的四个等式被存储在计算机可读介质中。 复阻抗的四个测量值被计算机代入四个存储的方程。 通过求解四个等式获得四个单独的RLC电路元件的值。 通过使用优化例程获得四个未知值，然后将其存储到计算机可读介质中。 然后显示表示DUT的电容的值电容器元件。

公开(公告)号：US5773317A

公开(公告)日：1998-06-30

申请号：US572944

申请日：1995-12-15

Applicant: Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L2924/0002

Abstract: The use of a test chip having a wide channel MOSFETs of different channel widths and effective gate lengths allows for an experimental determination of the fringe capacitance per unit width. The use of channel widths greater than 100 microns increases the accuracy of the measured capacitance values.

Abstract translation: 使用具有不同沟道宽度和有效栅极长度的宽沟道MOSFET的测试芯片允许对每单位宽度的边缘电容进行实验测定。 使用大于100微米的通道宽度会增加测量电容值的精度。

公开(公告)号：US5770892A

公开(公告)日：1998-06-23

申请号：US460494

申请日：1995-06-02

Applicant: Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

Inventor： Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11

CPC classification number: H01L28/20 ,  H01L27/0605 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Abstract translation: CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。 在该多晶硅信号线内制造场效应器件。 场效应器件的沟道通过薄栅极介质与衬底中的有源区域分离，衬底内的有源区域用作场效应器件的控制栅极。 这种器件可用于提供用于CMOS SRAM单元的多晶硅P沟道晶体管。

公开(公告)号：US5371041A

公开(公告)日：1994-12-06

申请号：US831089

申请日：1992-02-07

Applicant: Fu-Tai Liou ,  Robert O. Miller ,  Mohammed M. Farohani ,  Yu-Pin Han

Inventor： Fu-Tai Liou ,  Robert O. Miller ,  Mohammed M. Farohani ,  Yu-Pin Han

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76856 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S148/147 ,  Y10S257/915

Abstract: A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).

Abstract translation: 用于在半导体结构中形成两层之间的连接的方法包括首先通过绝缘层（12）形成VIA（14）到下面的结构（10）。 侧壁间隔件（22）和（24）形成在VIA（14）的垂直壁上。 间隔件（22）和（24）具有锥形表面。 然后在VIA的底表面上形成阻挡层（30），随后CVD沉积WSi2的导电层（32）以提供保形导电层。 然后通过物理气相沉积技术沉积铝层（38），层（32）的下降部分在VIA（14）中的铝层（38）和下结构（10）之间提供导电连接。