发明授权
- 专利标题: Synchronizing circuit for an external signal and an internal sampling clock signal
- 专利标题(中): 外部信号同步电路和内部采样时钟信号
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申请号: US184394申请日: 1988-04-21
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公开(公告)号: US4943857A公开(公告)日: 1990-07-24
- 发明人: Nobuaki Izuno , Yasuo Kurosu , Koichi Okazawa , Yoshihiro Yokoyama , Kensuke Ooyu
- 申请人: Nobuaki Izuno , Yasuo Kurosu , Koichi Okazawa , Yoshihiro Yokoyama , Kensuke Ooyu
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX62-102625 19870424; JPX62-286738 19871113
- 主分类号: H03L7/081
- IPC分类号: H03L7/081 ; H04N5/04
摘要:
A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.