发明授权
US4943857A Synchronizing circuit for an external signal and an internal sampling clock signal 失效
外部信号同步电路和内部采样时钟信号

Synchronizing circuit for an external signal and an internal sampling
clock signal
摘要:
A video signal and a horizontal synchronizing signal provided from a work station are delayed by a plurality of delay circuits having different delay amounts, and phase differences between a sampling clock signal and the delayed signals are detected. A clock generator generates two kinds of clock pulses having opposite phases and the same frequency. A clock selector selects one of the clock pulses as a sampling pulse signal in response to the phase differences. Further, a phase difference between the horizontal synchronizing signal and the video signal is detected so that the phase difference between the horizontal synchronizing signal and the video signal is maintained constant.
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